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    • 8. 发明专利
    • Transistor, its fabrication process, and substrate for electrooptical device
    • 晶体管,其制造工艺和电极器件的衬底
    • JP2006278358A
    • 2006-10-12
    • JP2005090317
    • 2005-03-28
    • Seiko Epson Corpセイコーエプソン株式会社
    • SHIMADA HIROYUKI
    • H01L21/336H01L29/786
    • H01L29/78621H01L21/26586H01L29/66757H01L29/78666
    • PROBLEM TO BE SOLVED: To provide a transistor which can be scaled down while exhibiting sufficient breakdown voltage, and to provide its fabrication process and a substrate for electrooptical device.
      SOLUTION: The transistor comprises an insulating substrate 10, a semiconductor film including a channel region 100 and source and drain regions 40a, 40b formed on the insulating substrate 10, and a gate electrode 32 provided on the channel region 100. The semiconductor film has lightly doped low concentration regions 70a and 70b between the channel region 100 and the source and drain regions 40a, 40b. The source and drain regions 40a, 40b include a high concentration region which is doped heavily as compared with the low concentration regions 70a and 70b. At least a part of the low concentration regions 70a and 70b is formed at least partially on the inner wall face of trenches 10a and 10b formed in the insulating substrate 10.
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供可以在显示足够的击穿电压的同时按比例缩小的晶体管,并提供其制造工艺和用于电光器件的衬底。 晶体管包括绝缘基板10,包括沟道区域100的半导体膜以及形成在绝缘基板10上的源极和漏极区域40a,40b以及设置在沟道区域100上的栅极32.半导体 膜在沟道区域100和源极区域和漏极区域40a,40b之间具有轻掺杂的低浓度区域70a和70b。 源极区域和漏极区域40a,40b包括与低浓度区域70a和70b相比被重掺杂的高浓度区域。 至少部分低浓度区域70a和70b至少部分地形成在形成在绝缘基板10中的沟槽10a和10b的内壁面上。(C)2007,JPO&INPIT