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1. 发明专利

JP3563768B2 Rom program changing device 失效
公开(公告)号：JP3563768B2
公开(公告)日：2004-09-08
申请号：JP11825094
申请日：1994-05-31
申请人：株式会社ルネサステクノロジ
发明人：理細谷
IPC分类号： G06F11/28 , G06F9/06 , G06F9/26 , G06F9/445 , G06F11/00
CPC分类号： G06F9/328 , G06F8/66 , G06F9/268

2. 发明专利

JPS61131126A Information processing unit 失效
标题翻译：信息处理单元
公开(公告)号：JPS61131126A
公开(公告)日：1986-06-18
申请号：JP25334484
申请日：1984-11-30
申请人： Toshiba Corp
发明人： SAKATA KUNIHIKO , SAKAMOTO TSUTOMU
IPC分类号： G06F9/22 , G06F9/26
CPC分类号： G06F9/268
摘要： PURPOSE:To set plural intermission points by dividing equally an area of a control storage device, providing a brake address register corresponding to each area and intermitting the operation depending on the coincidence between the content of the register and that of an address register. CONSTITUTION:In the operation intermitting a microprogram, four addresses are prepared and they constitute a brake address register group (BAR) 3. The four address correspond respectively to areas being four equal division of the control storage device 1. Since the area of the control storage device 1 is decided by a high-order 2-bit of the address of the register 2, the selector 4 is switched by the high-order 2-bit and the content of the BAR 3 corresponding to the area is inputted to a comparator 5. The comparator 5 compares the content with the content of the register 2, and when they are coincident, the brake point signal is true to intermit the operation of the microprogram.
摘要翻译：目的：通过平均分配控制存储装置的区域来设置多个中断点，提供对应于每个区域的制动地址寄存器，并根据寄存器的内容与地址寄存器的内容之间的一致性来中断该操作。构成：在中断微程序的操作中，准备了四个地址，它们构成制动地址寄存器组（BAR）3。四个地址分别对应于控制存储装置1的四等分的区域。由于控制区域存储装置1由寄存器2的地址的高位2位决定，选择器4被高位2位切换，并且与区域相对应的BAR 3的内容被输入到比较器比较器5将内容与寄存器2的内容进行比较，并且当它们重合时，制动点信号为真，以间断微程序的操作。

3. 发明专利

JPS61112238A Microprogram control system for data processor 失效
标题翻译：数据处理器微控制系统
公开(公告)号：JPS61112238A
公开(公告)日：1986-05-30
申请号：JP23242284
申请日：1984-11-06
申请人： Nec Corp
发明人： TAKANO TADASHI
IPC分类号： G06F9/22 , G06F9/26
CPC分类号： G06F9/328 , G06F9/268
摘要： PURPOSE:To facilitate the easy correction processing by branching a signal to the 2nd memory means when the coincidence is obtained between the microinstruction address set to the 1st microinstruction address memory means and the microinstruction memory address. CONSTITUTION:The microinstruction set addresses which receive the output of a microprocessor part 21 and stores the address of a microinstruction changing part and the contents of correction of the microinstruction are set to microinstruction address memory registers 24 and 25. A microinstruction address control part 22 compares the storage address of a microprogram to be read out next with the contents of the register 24 through a comparator 26. When the coincidence of this comparison is detected by a coincidence detecting circuit 27, a selector 23 selects and delivers a signal AR2. Then the actuation of a microprocessor part 21 is invalidated. At the same time, the writing is carried out to a microinstruction return address register provided in the part 22.
摘要翻译：目的：当在设置到第一微指令地址存储装置的微指令地址和微指令存储器地址之间获得一致时，便于通过将信号分支到第二存储器装置来简化校正处理。构成：微指令集地址接收微处理器部分21的输出并存储微指令改变部分的地址，微指令的校正内容被设置到微指令地址存储寄存器24和25.微指令地址控制部分22比较接下来要通过比较器26读出寄存器24的内容的微程序的存储地址。当由一致检测电路27检测到该比较的一致时，选择器23选择并传送信号AR2。然后微处理器部分21的致动无效。同时，写入到第22部分提供的微指令返回地址寄存器。

4. 发明专利

JPS59186062A Decentralized processor system 失效
标题翻译：分散处理器系统
公开(公告)号：JPS59186062A
公开(公告)日：1984-10-22
申请号：JP6114883
申请日：1983-04-07
申请人： Nec Corp
发明人： HORIKAWA AKINORI
IPC分类号： G06F15/16 , G06F9/26 , G06F9/38 , G06F9/52 , G06F13/36 , G06F15/177
CPC分类号： G06F9/3824 , G06F9/268 , G06F9/3867 , G06F13/36
摘要： PURPOSE: To reduce the amount of hardware by providing a specific command generating means to an instruction step being one step before a microinstruction step where bus acquisition competition might be caused between an execution processor and a decoding processor.
CONSTITUTION: A command 24 is decoded by a command decoder 6 and if the command 24 is a pause command, the decoder 6 stops the 2nd clock 26 from a clock control circuit 7. That is, a pause command 24 is generated at the microinstruction cycle being one step before the instruction cycle where the microinstruction in the execution processor U2 transferring data from a register file 18 to a register 19 and the microinstruction C in the decoding processor U1 attended with the use of a bus 12 are overlapped. In this case, the 2nd clock 26 keeps a high level state.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过向指令步骤提供特定命令生成手段来减少硬件数量，该指令步骤是在执行处理器和解码处理器之间可能引起总线获取竞争的微指令步骤之前的一个步骤。构成：命令解码器6解码命令24，如果命令24是暂停命令，则解码器6从时钟控制电路7停止第二时钟26.也就是说，在微指令周期产生暂停命令24 在执行处理器U2中的将微处理器U2从寄存器文件18传送到寄存器19的微指令和解码处理器U1中的微指令C与使用总线12相结合的指令周期之间的一个步骤是重叠的。在这种情况下，第二时钟26保持高电平状态。

5. 发明专利

JPS59112346A Information processor 失效
标题翻译：信息处理器
公开(公告)号：JPS59112346A
公开(公告)日：1984-06-28
申请号：JP22186082
申请日：1982-12-20
申请人： Hitachi Ltd
发明人： KOBAYASHI KUMIKO , YAMAOKA HIROMASA
IPC分类号： G06F9/22 , G06F9/26
CPC分类号： G06F9/328 , G06F9/268
摘要： PURPOSE:To execute different processing in accordance with each object by specifying an optional part of a program to be changed without changing the program itself. CONSTITUTION:A comparator 12 and an address buffer 13 are prepared to constitute a microprogram 14 controlling a microprogram counter 10. Microprogram memories 11a, 11b are also provided. A program counter 7a in a register RALU7 of arithmetic and logic circuit sets up an initial value in the buffer 13 and stores the address value in the comparator 12 through a transfer bus 15a. The value of the comparator 12 is compared with that of the buffer 13 and AND of both values is found to determine the counter 10. The contents of the program memory 11a or 11b are processed by the value of the counter 10.
摘要翻译：目的：通过指定要更改的程序的可选部分，根据每个对象执行不同的处理，而不改变程序本身。构成：准备比较器12和地址缓冲器13，以构成控制微程序计数器10的微程序14。还提供了微程序存储器11a，11b。算术和逻辑电路的寄存器RALU7中的程序计数器7a在缓冲器13中建立初始值，并通过传输总线15a将比较器12中的地址值存储。将比较器12的值与缓冲器13的值进行比较，并且发现两个值的“与”来确定计数器10.程序存储器11a或11b的内容由计数器10的值进行处理。

6. 发明专利

JPS59109950A Error processing system of control storage device 失效
标题翻译：控制存储设备的错误处理系统
公开(公告)号：JPS59109950A
公开(公告)日：1984-06-25
申请号：JP21972782
申请日：1982-12-15
申请人： Mitsubishi Electric Corp
发明人： NISHIDA KENJI
IPC分类号： G06F12/16 , G06F9/26
CPC分类号： G06F9/268
摘要： PURPOSE:To change easily the contents of a control storage, and to simplify a validity check by changing a parity bit storage device of a control storage device of a data processing device so as to be rewritable, and rewriting it by a micro-instruction. CONSTITUTION:When a power source is turned on to a device, a mode control device 29 of a parity check is set to a parity generating mode, and a value of a parity bit added to a read-only memory device 21 by a micro-instruction is written successively in a parity bit storage device 22. Subsequently, when the mode controlling circuit 29 of a parity check is set to a parity check mode, and an address of the parity bit storage device 22 in which an erroneous parity bit is written is read out, a parity error is detected by a parity checking circuit 23, and a parity error signal 25 is generated.
摘要翻译：目的：通过改变数据处理装置的控制存储装置的奇偶校验位存储装置进行可重写，并通过微指令重写来简化控制存储器的内容，简化有效性检查。构成：当电源接通装置时，奇偶校验的模式控制装置29被设置为奇偶校验生成模式，并且通过微处理器将奇偶校验位的值加到只读存储器装置21，指令被顺序写入奇偶校验位存储装置22.随后，当奇偶校验的模式控制电路29被设置为奇偶校验模式时，以及奇偶校验位存储装置22的写入错误奇偶校验位的地址读出，奇偶校验电路23检测出奇偶校验错误，产生奇偶校验错误信号25。

7. 发明专利

JPS5947647A Microprogram controller 失效
标题翻译：微控制器
公开(公告)号：JPS5947647A
公开(公告)日：1984-03-17
申请号：JP6780582
申请日：1982-04-22
申请人： Hitachi Ltd
发明人： IKEDA KOUICHI , MIMURA KAZUNOBU , OKABE TOSHIHIRO
IPC分类号： G06F9/22 , G06F9/26 , G06F11/28
CPC分类号： G06F9/268
摘要： PURPOSE:To attain a function in the modes other than a normal mode without decelerating the instruction processing speed in the normal mode, by processing the same instructions as different ones between the normal mode and other modes excepting the normal mode. CONSTITUTION:An instruction read out of an instruction storage device 1 is stored in an instruction register RG2. The 4 bits of an instruction code part is added to the 1-bit information of a state information storage RG3 and then set to the upper 5 bits of a CS address RG5 via a CS address producing circuit 4 for microprogram storing memory. While a logical value 0 is set to lower 3 bits, and 0 and 1 are set to the RG3 in a normal mode and a debug mode respectively. The contents of an RG5 are replaced by an address replacing circuit 7 to execute a mu program after one step of the mu program of a CS6 shown by the RG5 is executed. It is possible to execute different mu programs by the state information of the RG3 and between a normal mode and another mode other than the normal mode even for the same instruction.
摘要翻译：目的：通过处理与正常模式和正常模式以外的其他模式之间的不同的指令，通过处理与正常模式不同的指令，在正常模式以外的模式下实现功能，而不减速正常模式下的指令处理速度。构成：从指令存储装置1读出的指令存储在指令寄存器RG2中。指令代码部分的4位被添加到状态信息存储器RG3的1位信息，然后经由用于微程序存储存储器的CS地址产生电路4设置到CS地址RG5的高5位。当逻辑值0被设置为低3位时，分别在正常模式和调试模式下将0和1设置为RG3。由RG5所示的CS6的mu程序的一步执行后，RG5的内容由地址替换电路7代替执行mu程序。即使对于相同的指令，也可以通过RG3的状态信息和普通模式与正常模式之外的另一模式执行不同的mu程序。

8. 发明专利

JPS5769454A Microprogram controller 失效
标题翻译：微控制器
公开(公告)号：JPS5769454A
公开(公告)日：1982-04-28
申请号：JP14464180
申请日：1980-10-16
申请人： Mitsubishi Electric Corp
发明人： YOSHIDA SHIYUNICHI
IPC分类号： G06F9/22 , G06F9/26
CPC分类号： G06F9/328 , G06F9/268
摘要： PURPOSE:To eliminate the need to modify a hardward, by rewriting the contents of a random access memory when entrance addresses of a microprogram excuting machine language instructions are changed owing to the modification of the microprogram. CONSTITUTION:For the rewriting of the contents of a rewritable random access memory 3 for decoding, the address of the memory 3 is read out of a main storage device 1 by a microprogram and stored in a register 2, and the output of the register 2 is supplied as the write-in address of the memory 3 to the memory 3; and data to be written in the said address is read out of the device 1 and supplied to the memory 3 via a write data line, and a signal is supplied to a write control line 8 by the microprogram, thus permitting writing operation. Consequently, the contents of a decoder is rewritten, so it is unnecessary to modify hardware even when the entrance address of the microprogram are changed owing to the modification of the microprogram.
摘要翻译：目的：通过改写微程序来改变微程序排除机器语言指令的入口地址而改变随机存取存储器的内容，以消除需要修改的难度。构成：为了重写用于解码的可重写随机存取存储器3的内容，存储器3的地址通过微程序从主存储装置1中读出并存储在寄存器2中，并且寄存器2的输出作为存储器3的写入地址提供给存储器3; 将要写入所述地址的数据从设备1中读出并通过写入数据线提供给存储器3，并且通过微程序将信号提供给写入控制线8，从而允许写入操作。因此，解码器的内容被重写，因此即使当微程序的入口地址由于微程序的修改而改变时，也不需要修改硬件。

9. 发明专利

JPS61139835A Microprogram overlay system 失效
标题翻译：麦克风覆盖系统
公开(公告)号：JPS61139835A
公开(公告)日：1986-06-27
申请号：JP26144384
申请日：1984-12-11
申请人： Nec Corp
发明人： CHIWAKI YOSHINORI
IPC分类号： G06F9/24 , G06F9/22 , G06F9/26
CPC分类号： G06F9/328 , G06F9/268
摘要： PURPOSE:To load an overlay part with a small amount of hardware by using a shift path provided for diagnosis to load a microprogram. CONSTITUTION:Contents of an overlay address register 3 are compared in a comparator 4; and if it is judged that overlay is necessary, a new overlay address is set to an overlay register 5, and a holding signal is outputted to stop the data processing. When an overlay request signal comes to a diagnosing part 8, a write pulse control part 81 included in this part 8 loads a required overlay part in an overlay memory 84 to a shift register 82 in accordance with the overlay address signal and uses the shift path to set it to an address register 1 and a write data register 2. A shift path control part 83 repeats this operation to load all of the overlay part to a control storage part 6 and restarts the processing.
摘要翻译：目的：通过使用为诊断提供的移位路径加载微程序来加载少量硬件的覆盖部分。构成：在比较器4中比较覆盖地址寄存器3的内容; 并且如果判断需要覆盖，则将新的覆盖地址设置到覆盖寄存器5，并输出保持信号以停止数据处理。当覆盖请求信号到达诊断部分8时，包括在该部分8中的写入脉冲控制部分81根据覆盖地址信号将重叠存储器84中的所需覆盖部分加载到移位寄存器82，并使用移位路径将其设置为地址寄存器1和写入数据寄存器2.移位路径控制部分83重复该操作以将所有覆盖部分加载到控制存储部分6并重新开始处理。

10. 发明专利

JPS61118838A Microprogrammable system 失效
标题翻译：微生物系统
公开(公告)号：JPS61118838A
公开(公告)日：1986-06-06
申请号：JP23314185
申请日：1985-10-18
申请人： Honeywell Inf Systems
发明人： RICHIYAADO PII KERII , TOOMASU EFU JIYOISU
IPC分类号： G06F9/22 , G06F9/26 , G06F9/28
CPC分类号： G06F9/26 , G06F9/268 , G06F9/28

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