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1. 发明专利

JP5063850B2 Method and apparatus for the test coverage maximize 有权
公开(公告)号：JP5063850B2
公开(公告)日：2012-10-31
申请号：JP2002501058
申请日：2001-06-03
申请人：ベリシティリミテッド
发明人：アモスノイ，
IPC分类号： G01R31/3183 , G01R31/28 , G01R31/317 , G06F17/50
CPC分类号： G01R31/31707 , G01R31/31835

2. 发明专利

JP2009092437A Test pattern evaluation method and device 有权
标题翻译：测试模式评估方法和设备
公开(公告)号：JP2009092437A
公开(公告)日：2009-04-30
申请号：JP2007261333
申请日：2007-10-04
申请人： Sharp Corp , シャープ株式会社
发明人： KUCHII TOSHIMASA
IPC分类号： G01R31/3183 , G06F17/50
CPC分类号： G06F17/5022 , G01R31/31835
摘要： PROBLEM TO BE SOLVED: To provide a test pattern evaluation method and an evaluation device capable of performing evaluation in a reliability test accurately and properly, while reducing a simulation time, by a simulator having a gate level having comparatively short simulation time, or higher.
SOLUTION: It is assumed that each possible internal state of a cell determined at least by a logic value or a voltage value of an input terminal is a cell state, and each possible state of a transistor determined by a voltage between terminals is a transistor state. The method includes: a cell state acquisition process for verifying operation of a semiconductor integrated circuit at a gate level or higher, and acquiring an appearance cell state continuously appearing for a predetermined time or more in the operation verification; a transistor state acquisition process for acquiring an appearance transistor state using the corresponding appearance cell state in the operation verification for each transistor; and a test activity calculation process for calculating a test activity ratio of the transistor using the corresponding appearance transistor state for each transistor.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种能够通过具有比较短的模拟时间的门级的模拟器，同时在减少模拟时间的同时，在可靠性测试中进行可靠性测试的评估的测试模式评估方法和评估装置，或更高。解决方案：假设至少由输入端子的逻辑值或电压值确定的单元的每个可能的内部状态是单元状态，并且由端子之间的电压确定的晶体管的每个可能状态是晶体管状态。该方法包括：在门级或更高级别验证半导体集成电路的操作的单元状态获取处理，以及在操作验证中获取连续出现预定时间或更长时间的外观单元状态; 晶体管状态获取处理，用于在每个晶体管的操作验证中使用对应的出现单元状态获取外观晶体管状态; 以及测试活动计算处理，用于使用每个晶体管的相应外观晶体管状态来计算晶体管的测试活动比。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP4182202B2 Coverage calculating device and simulation coverage calculating method for simulation 有权
公开(公告)号：JP4182202B2
公开(公告)日：2008-11-19
申请号：JP2002225523
申请日：2002-08-02
申请人：富士通マイクロエレクトロニクス株式会社
发明人：健志安倍 , 秀樹磯部
IPC分类号： G06F17/50 , G01R31/28 , G01R31/3183
CPC分类号： G01R31/31835

4. 发明专利

JP2004119963A Method for optimizing test based on experiential data 审中-公开
标题翻译：基于经验数据优化测试的方法
公开(公告)号：JP2004119963A
公开(公告)日：2004-04-15
申请号：JP2003295406
申请日：2003-08-19
申请人： Agilent Technol Inc , アジレント・テクノロジーズ・インクAgilent Technologies, Inc.
发明人： STIRRAT SUSAN , WU KANG
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3183 , H01L21/66
CPC分类号： G01R31/31835 , G01R31/2894
摘要： PROBLEM TO BE SOLVED: To contrive the efficiency of defect detection tests of integrated circuits, using a test planning method. SOLUTION: This method is a method for optimizing test for integrated circuits, and is a step of executing a first test procedure comprising a plurality of tests generating statistically crucial test results, comprising one or more defective test results through testing a plurality of first integrated circuits. This method is characterized by having a step of executing a first test procedure causing no shutdown, even when one or more defective test results of a plurality of first integrated circuits are generated during its execution period; a step of analyzing one or more defective test results and specifying one or more redundant and inefficient tests during a plurality of tests of the first test procedure; and a step of generating a second test procedure optimized for the first test procedure, by executing at least one of exclusion or rearrangement with respect to at least one or more redundant and inefficient tests. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：使用测试计划方法来设计集成电路的缺陷检测测试的效率。解决方案：该方法是用于优化集成电路的测试的方法，并且是执行第一测试过程的步骤，该测试程序包括产生统计上至关重要的测试结果的多个测试，包括一个或多个缺陷测试结果，通过测试多个第一集成电路。该方法的特征在于，即使在其执行期间产生多个第一集成电路的一个或多个有缺陷的测试结果，也具有执行不关闭的第一测试过程的步骤; 在第一测试程序的多个测试期间分析一个或多个有缺陷的测试结果并指定一个或多个冗余且低效的测试的步骤; 以及生成针对第一测试程序优化的第二测试过程的步骤，通过相对于至少一个或多个冗余和低效测试执行排除或重排中的至少一个。版权所有（C）2004，JPO

5. 发明专利

JP2003036183A Method for testing integrated circuit using integrated debugging circuit 审中-公开
标题翻译：使用集成调试电路测试集成电路的方法
公开(公告)号：JP2003036183A
公开(公告)日：2003-02-07
申请号：JP2002139368
申请日：2002-05-15
申请人： Hewlett Packard Co , ヒューレット・パッカード・カンパニー
发明人： IMARK ROBERT R , BERKRAM DANIEL A
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3183 , G06F11/22 , G06F11/26
CPC分类号： G06F11/261 , G01R31/31705 , G01R31/31835
摘要： PROBLEM TO BE SOLVED: To provide a testing method capable of integrating microprocessor test input with test hardware input. SOLUTION: This method simulates an integrated circuit 110 and generates an input vector to an integrated circuit 110 and expected output from the integrated circuit. This input vector and expected output are generated by entering test vectors into the circuit simulator and the integrated circuit is tested using the input vector 113 to yield a first resulting output. The test hardware vector 109 is also created to capture state information pertaining to the integrated circuit. The test hardware vector and the input vector are combined to create a joint input vector 111 and debugging is performed on the integrated circuit by modifying the joint input vector and evaluating the resulting output.
摘要翻译：要解决的问题：提供能够将微处理器测试输入与测试硬件输入集成的测试方法。解决方案：该方法模拟集成电路110，并向集成电路110产生输入向量，并从集成电路产生期望的输出。通过将测试矢量输入到电路仿真器中来生成该输入矢量和预期输出，并且使用输入矢量113测试集成电路以产生第一结果输出。还创建测试硬件向量109以捕获属于集成电路的状态信息。组合测试硬件向量和输入向量以创建联合输入向量111，并通过修改关节输入向量并对所得到的输出进行评估，对集成电路进行调试。

6. 发明专利

JP2011112434A Method for inserting test point for logic circuit and logic circuit test apparatus 审中-公开
标题翻译：插入逻辑电路和逻辑电路测试装置测试点的方法
公开(公告)号：JP2011112434A
公开(公告)日：2011-06-09
申请号：JP2009267386
申请日：2009-11-25
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： HARADA EIJI
IPC分类号： G01R31/28 , G01R31/3183 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G01R31/31835 , G06F11/267
摘要： PROBLEM TO BE SOLVED: To effectively insert a test point into a logic circuit of a tested object.
SOLUTION: The logic circuit test apparatus 10 includes a failure estimation section 110 estimating a failure estimation degree of a signal line by a wiring condition obtained from design data of the logic circuit. The logic circuit test apparatus 10 also includes an insertion section 130 inserting the test point based on the failure estimation degree. The logic circuit test apparatus 10 performs a test for the logic circuit into which the test point is inserted by the insertion section 130.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：有效地将测试点插入测试对象的逻辑电路中。解决方案：逻辑电路测试装置10包括故障估计部分110，通过由逻辑电路的设计数据获得的布线条件来估计信号线的故障估计度。逻辑电路测试装置10还包括基于故障估计度插入测试点的插入部分130。逻辑电路测试装置10对插入部分130插入测试点的逻辑电路进行测试。版权所有：（C）2011，JPO＆INPIT

7. 发明专利

JP4602004B2 Test pattern generation apparatus, test pattern generation method and test pattern generation program 有权
公开(公告)号：JP4602004B2
公开(公告)日：2010-12-22
申请号：JP2004184177
申请日：2004-06-22
申请人：株式会社東芝
发明人：泰幸野津山
IPC分类号： G01R31/3183 , G01R31/28 , G06F17/50
CPC分类号： G01R31/31835

8. 发明专利

JP2008268062A Test pattern generation, failure detection rate calculating device, test pattern generation, and failure detection rate calculation method 有权
标题翻译：测试模式生成，故障检测速率计算设备，测试模式生成和故障检测速率计算方法
公开(公告)号：JP2008268062A
公开(公告)日：2008-11-06
申请号：JP2007112914
申请日：2007-04-23
申请人： Toshiba Corp , 株式会社東芝
发明人： NOTSUYAMA YASUYUKI
IPC分类号： G01R31/3183
CPC分类号： G01R31/31835
摘要： PROBLEM TO BE SOLVED: To improve the quality of testing by generating a test pattern which detects bridge failures of LSI, with high accuracy. SOLUTION: A failure detection rate calculation device includes a bridge failure potential calculation part for generating bridge failure potential information indicating the relation of an input logic value of a cell and potential on a bridge presumed on an output terminal; a logic threshold calculating part 102 for calculating the logic threshold of an input terminal; a bridge failure information extracting part 104 for extracting bridge failure information; a detection limit resistance value calculating part 103 for generating enlargement bridge failure potential information, by calculating the detection limit resistance value of each bridge failure; a bridge failure list generating part 105 for generating a bridge failure list; a test pattern generating part 106 for generating the test pattern and failure detection information, based on the bridge failure list; and a failure detection rate calculating part 107 for calculating weighted failure detection rate and a bridge remaining rate, or the like, based on failure detection information and bridge failure occurrence information. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过以高精度生成检测LSI的桥接故障的测试图案来提高测试质量。解决方案：故障检测率计算装置包括桥接故障电位计算部分，用于产生指示单元的输入逻辑值与假设在输出端上的桥上的电位的关系的桥故障电位信息; 逻辑阈值计算部分102，用于计算输入终端的逻辑门限; 用于提取桥故障信息的桥故障信息提取部104; 用于通过计算每个桥式故障的检测极限电阻值来产生放大桥故障电位信息的检测限电阻值计算部103; 用于生成桥故障列表的桥故障列表生成部105; 基于桥接故障列表生成测试模式和故障检测信息的测试模式生成部106; 以及故障检测率计算部107，用于基于故障检测信息和桥接故障发生信息来计算加权故障检测率和桥剩余率等。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2007120991A Detection rate calculation method of test pattern, computer program, and detection rate calculation device of test pattern 审中-公开
标题翻译：测试图案，计算机程序和检测速率计算方法的检测速率计算方法
公开(公告)号：JP2007120991A
公开(公告)日：2007-05-17
申请号：JP2005310293
申请日：2005-10-25
申请人： Sharp Corp , シャープ株式会社
发明人： NAKAJIMA YUKITAKA
IPC分类号： G01R31/3183 , H01L21/82
CPC分类号： G06F17/5036 , G01R31/31835
摘要： PROBLEM TO BE SOLVED: To provide a detection rate calculation method of a test pattern for calculating the degree of detection by the test pattern of a short-circuit failure generated between adjacent wires in a semiconductor integrated circuit, and also to provide a computer program and a detection rate calculation device of the test pattern, which execute the method and show the detection rate to a designer.
SOLUTION: A layout generation program 12 generates layout data 25 from circuit data 21, and creates information of adjacent wires from the layout data 25 as adjacent wire information 24, and outputs the result. A transistor level simulation program 11 performs simulation by using the test pattern 22, and generates the electric potential of each wire in the circuit as electric potential information 23, and outputs it. A failure detection rate calculation program 13 checks whether the electric potential difference between adjacent wires is greater than a prescribed electric potential difference, from the adjacent wire information 24 and the electric potential information 23, and calculates the detection rate of the short-circuit failure, based on the result.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于通过在半导体集成电路中的相邻导线之间产生的短路故障的测试图案来计算检测程度的测试图案的检测率计算方法，并且还提供计算机程序和测试图案的检测率计算装置，其执行该方法并向设计者显示检测率。解决方案：布局生成程序12从电路数据21生成布局数据25，并从布局数据25创建相邻布线的信息作为相邻布线信息24，并输出结果。晶体管电平仿真程序11通过使用测试图案22进行仿真，并且产生电路中每根导线的电位作为电位信息23，并将其输出。故障检测率计算程序13从相邻的线信息24和电位信息23检查相邻线之间的电位差是否大于规定的电位差，并计算短路故障的检测率，基于结果。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2003535343A Method and apparatus for the test coverage maximize 有权
公开(公告)号：JP2003535343A
公开(公告)日：2003-11-25
申请号：JP2002501058
申请日：2001-06-03
申请人：ベリシティリミテッド
发明人：アモスノイ，
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3183 , G06F17/50
CPC分类号： G01R31/31707 , G01R31/31835
摘要： (57)【要約】テストカバレージのためのソフトウェアはカバレージの穴を自動的に識別し、これらの領域をテストするために入力プロセスを変更することによって改善される。好ましい実施形態では、テストは反復的に再実行されテストカバレージを改善し続ける。

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