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1. 发明专利

JPS6199411A Single pulse generating circuit 失效
标题翻译：单脉冲发生电路
公开(公告)号：JPS6199411A
公开(公告)日：1986-05-17
申请号：JP22093484
申请日：1984-10-20
申请人： Makoto Aso
发明人： ASO MAKOTO
IPC分类号： H03K3/02 , H03K5/04 , H03K17/28
CPC分类号： H03K17/28
摘要： PURPOSE:To prevent the malfunction due to external noise by outputting the output from a switch through the first resistance and charging a capacitor through the second resistance and turning off said output with a transistor (TR) which is operated with the terminal voltage of the capacitor. CONSTITUTION:When a switch 7 is closed, a TR 8 is turned on, and the collector current of the TR 8 passes a resistance 13 and turns on a TR 10 and charges a capacitor 9 through a resistance 12. When the voltage of the capacitor 9 becomes higher than a certain voltage, a TR 11 is switched to the turn-on state, and the TR 10 is turned off. The output having a preliminarily determined pulse width is obtained from the collector of the TR 10 even if the closing time of the switch 7 is long.
摘要翻译：目的：为了防止由外部噪音引起的故障，通过第一个电阻输出开关的输出，并通过第二个电阻对电容充电，并用晶体管（TR）关断所述输出，晶体管（TR）用电容器的端子电压。构成：当开关7闭合时，TR8导通，TR8的集电极电流通过电阻13并接通TR 10，并通过电阻12对电容器9充电。当电容器的电压 9变得高于一定电压，TR 11被切换到接通状态，并且TR 10被关断。即使开关7的闭合时间较长，也从TR 10的集电极获得预先确定的脉冲宽度的输出。

2. 发明专利

JPS59144221A Alternating current switch circuit 失效
标题翻译：交流电流开关电路
公开(公告)号：JPS59144221A
公开(公告)日：1984-08-18
申请号：JP1748383
申请日：1983-02-07
申请人： Makoto Aso
发明人： ASOU MAKOTO
IPC分类号： H03K17/725
CPC分类号： H03K17/725
摘要： PURPOSE:To turn on an AC voltage by one pulse and to hold this on state by holding enough charges to trigger a thyristor until a next half wave arrives from a rectifier. CONSTITUTION:The thyristor has a period wherein its current decreases below a holding current until the next half wave arrives after the 1st half wave arrives, but charges accumulated in a capacitor 17 supply a voltage and a current which are enough to trigger the thyristor 12 until the next half wave arrives from the rectifier 11. A resistance 14 for discharging accumulated carriers has a much less value than a resistance 15, so carriers accumulated in a voltage drop element 13 and a fine current flowing reversely from the capacitor 17 are discharged speedily. Therefore, while the current of the thyristor 12 decreases below the holding current, the gate-cathode voltage of this thyristor 12 is held above a trigger voltage. Thus, an alternating current flows through a load 10 for reception continuously once the thyristor 12 is triggered. Namely, the alternating current is turned on by one pulse and this ''on state'' is held.
摘要翻译：目的：通过保持足够的电荷来触发晶闸管，直到下一个半波从整流器到达，才能将交流电压接通一个脉冲并保持此状态。构成：晶闸管具有其电流降低到低于保持电流的时间，直到第一半波到达下一半波到达，但是累积在电容器17中的电荷提供足以触发晶闸管12的电压和电流直到下一半波从整流器11到达。用于对累积载流子进行放电的电阻14的值比电阻15小得多，所以积聚在电压降元件13中的载流子和从电容器17反向流动的微细电流被快速放电。因此，当晶闸管12的电流降低到保持电流以下时，该晶闸管12的栅极 - 阴极电压被保持在触发电压以上。因此，一旦触发了晶闸管12，交流电流就流过负载10以便连续接收。即，交流电被接通一个脉冲，并且保持“接通状态”。

3. 发明专利

JPS6141217A Delay circuit 失效
标题翻译：延时电路
公开(公告)号：JPS6141217A
公开(公告)日：1986-02-27
申请号：JP16332184
申请日：1984-08-01
申请人： Makoto Aso
发明人： ASO MAKOTO
IPC分类号： H03H11/26
CPC分类号： H03H11/26
摘要： PURPOSE:To decrease the number of component parts and to improve the rise or fall performance of a delay circuit by feeding positively a signal produced from the output signal of an FET back to the gate of the FET. CONSTITUTION:The drain potential of an FET1 is set approximately at 0V in an application mode of power supply. Therefore a Tr5 is kept OFF with the FET1 kept ON respectively. A capacitor 2 is charged continuously after application of the power supply. Then the Tr5 is turned ON when the drain potential of the FET1 gives the breakdown to a Zener diode 4. Thus the gate potential of the FET1 is also reduced. As a result, an electric field is applied to the FET1 to increase the internal impedance. Then the drain impedance of the FET1 rises up further. Thus the base current of the Tr5 flowing through the diode 4 is increased more. The Tr5 is turned ON suddenly owing to such a reproducing action. While the FET1 is suddenly turned OFF.
摘要翻译：目的：减少组件数量，并通过将FET的输出信号产生的信号反馈给FET的栅极，从而提高延迟电路的上升或下降性能。构成：在电源的应用模式下，FET1的漏极电位设置为0V。因此，将FET5保持ON时，Tr5保持OFF。在施加电源之后，电容器2被连续充电。然后当FET1的漏极电位给齐纳二极管4击穿时，Tr5导通。因此，FET1的栅极电位也降低。结果，向FET1施加电场以增加内部阻抗。然后FET1的漏极阻抗进一步上升。因此，流过二极管4的Tr5的基极电流增加。由于这种再现动作，Tr5突然开启。当FET1突然关闭时。

4. 发明专利

JPS6140695A Flicker circuit 失效
标题翻译：闪光电路
公开(公告)号：JPS6140695A
公开(公告)日：1986-02-26
申请号：JP16332284
申请日：1984-08-01
申请人： Makoto Aso
发明人： ASO MAKOTO
IPC分类号： G08B5/36

5. 发明专利

JPS6154873A Transformerless dc/dc converter 失效
标题翻译：无变压器DC / DC转换器
公开(公告)号：JPS6154873A
公开(公告)日：1986-03-19
申请号：JP17556584
申请日：1984-08-22
申请人： Makoto Aso
发明人： ASO MAKOTO
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： PURPOSE:To rise a DC voltage without using a transformer by changing and discharging two capacitors by the first and second transistors which are alternately turned ON and OFF and outputting the superposed voltage. CONSTITUTION:The first transistor 8 is provided to charge the first capacitor 2 through a diode 1 from a supply voltage +V, the charging voltage of the first capacitor 2 is superposed with the supply voltage +V to provide the second transistor 7 to charge the second capacitor 4. Thus, the both transistors 7, 8 can be alternately turned ON and OFF to charge the supply voltage +V to the capacitor 2, and further it is discharged to output the voltage raise to approx. double voltage.
摘要翻译：目的：通过交替接通和关闭并输出叠加电压的第一和第二晶体管改变和放电两个电容器来升高直流电压，而不使用变压器。构成：提供第一晶体管8以从电源电压+ V通过二极管1对第一电容器2充电，第一电容器2的充电电压与电源电压+ V叠加，以提供第二晶体管7对第第二电容器4.因此，两个晶体管7,8可以交替地导通和截止以向电容器2充电电源电压+ V，并且进一步放电以将电压升高到大约。双电压。

6. 发明专利

JPS6148218A Delay circuit 失效
标题翻译：延时电路
公开(公告)号：JPS6148218A
公开(公告)日：1986-03-08
申请号：JP17082284
申请日：1984-08-15
申请人： Makoto Aso
发明人： ASO MAKOTO
IPC分类号： H03H11/26
摘要： PURPOSE: To quicken the rising or falling of an output by giving a signal whose potential changes according to the elapse of time to a gate of an FET and feeding back positively a signal based on the output to the FET.
CONSTITUTION: When a switch 4 is closed, a capacitor 5 is charged via a resistor 10 and a gate potential of an FET1 rises. Then the drain potential of the FET1 descends and when a Zener diode 6 breaks down, a transistor (TR)7 transits of the ON-stage. Then a TR9 is turned on and a collector potential of the TR9 falls down. The collector potential is given to a load and also to a source of the FET1 to apply positive feedback. Thus, the descending speed of the drain potential of the FET1 is quickened, the FET1 is turned of quickly and TRs 7, 9 and turned on quickly.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过给FET输出一个信号，根据时间的长短向FET的栅极提供一个信号，从而加快输出的上升或下降，并根据FET的输出肯定反馈一个信号。构成：当开关4闭合时，电容器5通过电阻器10充电，FET1的栅极电位上升。然后，FET1的漏极电位下降，并且当齐纳二极管6故障时，晶体管（TR）7转换到导通阶段。然后TR9导通，TR9的集电极电位下降。集电极电位被赋予负载，并且还提供给FET1的源极以施加正反馈。因此，FET1的漏极电位的下降速度加快，FET1快速转动，TRs 7,9快速转动。

7. 发明专利

JPS6145621A Delay circuit 失效
标题翻译：延时电路
公开(公告)号：JPS6145621A
公开(公告)日：1986-03-05
申请号：JP16723084
申请日：1984-08-08
申请人： Makoto Aso
发明人： ASO MAKOTO
IPC分类号： H03H11/26
摘要： PURPOSE: To obtain a delay circuit excellent in leading and trailing edges by keeping a gate of a FET at a prescribed potential and grounding one end of a channel via a capacitor.
CONSTITUTION: When a switch 8 is closed, charging to a capacitor 3 is started through a resistor 4 and a FET1 and the source potential of the FET1 is increased. When a source potential approaches a gate potential, an electric field is fed to the FET1 and the drain potential of the FET1 rises earlier than the source potential. When the drain potential of the FET1 breaks down a Zener diode 5, a load current is obtained from a collector of a transistor 6.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过将FET的栅极保持在规定的电位并通过电容器对通道的一端进行接地，以获得前沿和后沿优异的延迟电路。构成：当开关8闭合时，通过电阻器4和FET1开始对电容器3的充电，并且FET1的源极电位增加。当源极电位接近栅极电位时，电场被馈送到FET1，并且FET1的漏极电势比源极电位上升。当FET1的漏极电位破坏齐纳二极管5时，从晶体管6的集电极获得负载电流。

8. 发明专利

JPS61112422A Delay circuit 失效
标题翻译：延时电路
公开(公告)号：JPS61112422A
公开(公告)日：1986-05-30
申请号：JP24679885
申请日：1985-11-01
申请人： Makoto Aso
发明人： ASO MAKOTO
IPC分类号： H03K5/13 , H03K17/042 , H03K17/28
CPC分类号： H03K17/04213 , H03K17/28
摘要： PURPOSE:To rise an output current at a high speed by feeding back positively a part of an output current to a time constant capacitor connected to a source of an FET in an on-delay delay circuit. CONSTITUTION:In turning on a switch 9, an N-FET-1 is turned on, a capacitor 4 is charged through a resistor 5 and an FET1 and the source potential of the FET1 rises. When the source potential approaches the gate potential after a prescribed time, the internal impedance of the FET starts increasing and when the drain potential breaks down a Zener diode 6, a base current of a transistor (TR) 7 flows and the TR7 is turned on. Its emitter current flows to the capacitor 4 at the same time and increases the internal imp-edance of the FET1, then the emitter current is arisen at a high speed by the positive feedback action.
摘要翻译：目的：通过将输出电流的一部分反馈到连接到导通延迟延迟电路中FET的源极的时间常数电容器来高速上升输出电流。构成：在接通开关9时，N-FET-1导通，电容器4通过电阻器5和FET1充电，FET1的源极电位上升。当源电位在规定时间后接近栅极电位时，FET的内部阻抗开始上升，当漏极电位破坏齐纳二极管6时，晶体管（TR）7的基极电流流过，TR7导通。其发射极电流同时流到电容器4，并增加了FET1的内部电位，然后通过正反馈作用在高速下产生发射极电流。

9. 发明专利

JPS60213120A Delay circuit 失效
标题翻译：延时电路
公开(公告)号：JPS60213120A
公开(公告)日：1985-10-25
申请号：JP6983284
申请日：1984-04-06
申请人： Makoto Aso
发明人： ASOU MAKOTO
IPC分类号： H03K17/28
CPC分类号： H03K17/28
摘要： PURPOSE:To improve the rise of an output and to expand a delay time by feeding back the collector current of the 1st transistor (TR) to the base of the 2nd TR having polarity different from that of the 1st TR. CONSTITUTION:When a switch 7 is closed, charge to a capacitor 9 through a high resistor 8 is started, and when the voltage between both the poles of the capacitor 9 reaches the sum of the Zener voltage of a Zener diode 10 and the forward drop voltage between the base and emitter of a TR11, current flows into the base of the TR11 and the collector current of the TR11 flows. Since the collector of the TR11 is connected to the base of a TR13 through a resistor 12, the collector current of the TR13 is amplified and made to flow into a load 14. At that time, the collector current of the TR13 is fed back to the base of the TR11 through a resistor 15.
摘要翻译：目的：通过将第一晶体管（TR）的集电极电流反馈到具有与第一TR的极性不同的第二TR的基极，来改善输出的上升并延长延迟时间。构成：当开关7闭合时，开始通过高电阻器8向电容器9充电，并且当电容器9的两极之间的电压达到齐纳二极管10的齐纳电压和正向压降 TR11的基极和发射极之间的电压，电流流入TR11的基极，TR11的集电极电流流动。由于TR11的集电极通过电阻器12连接到TR13的基极，所以TR13的集电极电流被放大并流入负载14.此时，TR13的集电极电流被反馈到 TR11的基极通过电阻器15。

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