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1. 发明专利

JPS58208833A OUTPUT CONTROL SYSTEM 失效
公开(公告)号：JPS58208833A
公开(公告)日：1983-12-05
申请号：JP9256782
申请日：1982-05-31
申请人： YOKOGAWA ELECTRIC WORKS LTD
发明人： UCHIIKE HISAYUKI , OGAWA TOSHIO , OOHASHI KOUZOU , SANO HIDEO , TAKIGISHI SHINICHI
IPC分类号： G06F13/14 , G05B7/02 , G05B9/03 , G05B23/00 , G06F11/20 , G06F11/267 , G06F15/16 , G06F15/177 , G06F19/00
摘要： PURPOSE:To always carry out a self-check, by applying the output signal supplied from an upper intelligence unit to plural redundant output devices and then reading out the check output of each output device to select an output device. CONSTITUTION:The same data is given to output devices 6 and 7 from an upper intelligence unit 11 via a communication line 2. These data are compared 65 and 75 with the output data of data bases 61 and 71 after held at the bases 61 and 71 and underwent D/A conversions 62 and 72 as well as A/D conversions 64 and 74 respectively. Then a rereading check is given to those data, and the check output is sent to the bases 61 and 71. Thus the reading is possible through the unit 11. The unit 11 transmits a selection signal and selects an output device 6, for example, after closing a switch 63. Then a switch 73 is opened to transmit an analog output to the load 54 from the D/A converting circuit 62. In such a way, all redundant circuits can always received a self-check in a simple way.

2. 发明专利

JPS58159103A DUPLEX ANALOG SIGNAL OUTPUT DEVICE 失效
公开(公告)号：JPS58159103A
公开(公告)日：1983-09-21
申请号：JP4350582
申请日：1982-03-18
申请人： YOKOGAWA ELECTRIC WORKS LTD
发明人： UCHIIKE HISAYUKI , OOHASHI KOUZOU
IPC分类号： G05B9/03
摘要： PURPOSE:To enable the on-line maintenance and to confirm the normal state of the output at the queuing side, by using a control board which works in accordance with the output set value, a comparator which compares said set value with actual output value and an FF circuit formed with combination of gates. CONSTITUTION:The output signals of NAND gates G1 and G2 are set at L and H respectively, and therefore SW1 and SW2 are made at sides A and B respectively. Under such conditions, output circuits 1 and 2 are set at the working side and the queuing side respectively. Here if the circuit 1 has a fault, the state of an FF circuit is switched. Accordingly the SW1 and SW2 are also switched to set the circuits 2 and 1 at the working side and the queuing side respectively. When the on-line maintenance is carried out, a connector is pulled out for maintenance of the circuit 1 at the working side. Thus the output signal of the gate G2 is inverted to L. Then the SW2 is made at the side A, and the circuit 2 takes charge of supply of the output.

3. 发明专利

JPS58134528A AD CONVERTING DEVICE 失效
公开(公告)号：JPS58134528A
公开(公告)日：1983-08-10
申请号：JP1674782
申请日：1982-02-03
申请人： YOKOGAWA ELECTRIC WORKS LTD
发明人： UCHIIKE HISAYUKI , OOHASHI KOUZOU
IPC分类号： H03M1/08 , H03M1/12
摘要： PURPOSE:To eliminate a common mode noise by performing sampling operation which synchronizes with a commercial power source frequency and regarding the sum of several sampled values as a final result. CONSTITUTION:Sampling is carried on 3X2 times within one cycle of the commercial power source frequency and sampled values are A/D-converted and summed up for one cycle. Then, the result is shifted to the LSB side by (2+n) digits. The number of times of the sampling depends upon the relation to the value of the reference voltage 7 of an A/D converter 6 and 6V is selected to eliminate the need for complex processing of the outut of an A/D converter 7. Now, if n=1 and the output of the A/D converter 6 consists of 12 bits, the processing output of a CPU10 consists of 15 bits and 1 is only added as the LSB to realize the value of an input voltage which is easy to handle directly. When the input voltage is 5V, 5,000 is outputted as 16-bit data.

5. 发明专利

JPS5623051A SIGNAL TRANSMISSION SYSTEM 失效
公开(公告)号：JPS5623051A
公开(公告)日：1981-03-04
申请号：JP9932679
申请日：1979-08-03
申请人： YOKOGAWA ELECTRIC WORKS LTD
发明人： OOHASHI KOUZOU
IPC分类号： G08C25/00 , H04L1/00
摘要： PURPOSE:To perform the transmission of digital signal with high accuracy, by specified signal processing if bit variation is present between the input and output. CONSTITUTION:Taking a look at the digital signal at the reception section RX, there might be slight bit variance among input digital signals due to the error in the D/A converter 70, transmission line 80, and A/D converter 90. If the error produced from this transmission system is less than n-bit, the effective bit of the digital signal fed to the transmission section TX is taken more than n+2-bit and n+1-bit or less is taken as ''0''. Further, to either one of the transmission section TX and the reception section RX at least, digital signal in which ''1'' at n-bit or less and ''0'' at n+1-bit or more are achieved is fed to the digital signal. Thus, the effect of carry and borrow on n+2-bit or more due to the variance in n-bit can be avoided.

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