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1. 发明专利

JP2013156944A Semiconductor storage 审中-公开
标题翻译：半导体存储
公开(公告)号：JP2013156944A
公开(公告)日：2013-08-15
申请号：JP2012019044
申请日：2012-01-31
申请人： Toshiba Corp , 株式会社東芝 , Toshiba Information Systems (Japan) Corp , 東芝情報システム株式会社
发明人： MORITA TAKEO , ICHIDA MAKOTO
IPC分类号： G06F12/00 , H03L7/085 , H03L7/093 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage with a signal generation unit capable of achieving a change of operation setting in a simple manner and at low cost.SOLUTION: A storage unit 31 is configured of semiconductor memory. A PLL circuit 49 generates signals for controlling the storage unit 31. A register 50 holds information for setting the frequency of the PLL circuit 49. A restart circuit 51 restarts the PLL circuit 49. A control unit 44 sets the information to the register 50, and supplies the restart circuit 51 with the start signals, and the restart circuit 51 restarts the PLL circuit 49 on the basis of the information set to the register 50.
摘要翻译：要解决的问题：提供具有能够以简单的方式和低成本实现操作设置改变的信号生成单元的半导体存储器。解决方案：存储单元31由半导体存储器构成。 PLL电路49产生用于控制存储单元31的信号。寄存器50保存用于设置PLL电路49的频率的信息。重新启动电路51重新启动PLL电路49.控制单元44将信息设置到寄存器50，并向再起动电路51提供起动信号，再起动电路51根据设定在寄存器50的信息重新启动PLL电路49。

2. 发明专利

JP2011181000A Controller, semiconductor memory device, and method for controlling semiconductor memory device 审中-公开
标题翻译：控制器，半导体存储器件以及用于控制半导体存储器件的方法
公开(公告)号：JP2011181000A
公开(公告)日：2011-09-15
申请号：JP2010046919
申请日：2010-03-03
申请人： Toshiba Corp , Toshiba Information Systems (Japan) Corp , 東芝情報システム株式会社 , 株式会社東芝
发明人： MORITA TAKEO
IPC分类号： G06F21/24
CPC分类号： G06F12/00 , G06F12/14
摘要： PROBLEM TO BE SOLVED: To provide a controller improved in memory access latency, compared with conventional methods, when confidential information subjected to obfuscation processing in a predetermined unit is accessed.
SOLUTION: The controller is equipped with: an obfuscated information generation circuit 201 for generating obfuscated information on the basis of address information including an access address; an obfuscated information holding circuit 202 for holding the obfuscated information; an encoding/decoding circuit 203 for encoding or decoding data designated by the access address, by using the obfuscated information associated with the access address in the obfuscated information holding circuit 202; and an address/obfuscated-information associating circuit 204 which manages obfuscated information in association with an address serving as a base of the obfuscated information, and determines, in response to an access request, whether an access address in the access request agrees with the address serving as the base of the obfuscated information in the obfuscated information holding circuit 202, and controls, on the basis of a determination result, whether it is necessary to generate the obfuscated information, and whether the held obfuscated information should be used.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：与常规方法相比，当访问在预定单元中进行模糊处理的机密信息时，提供改进的存储器访问等待时间的控制器。解决方案：控制器配备有：用于根据包括访问地址的地址信息产生混淆信息的混淆信息生成电路201; 用于保存混淆信息的混淆信息保持电路202; 编码/解码电路203，用于通过使用与混淆信息保持电路202中的访问地址相关联的混淆信息对由访问地址指定的数据进行编码或解码; 以及地址/模糊化信息关联电路204，其与用作混淆信息的基础的地址相关联地管理混淆信息，并且响应于访问请求确定访问请求中的访问地址是否与地址一致作为混淆信息保持电路202中的混淆信息的基础，并且基于确定结果来控制是否需要生成混淆信息，以及是否应该使用保持的混淆信息。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2012128627A Data transfer system 审中-公开
标题翻译：数据传输系统
公开(公告)号：JP2012128627A
公开(公告)日：2012-07-05
申请号：JP2010279006
申请日：2010-12-15
申请人： Toshiba Corp , Toshiba Information Systems (Japan) Corp , 東芝情報システム株式会社 , 株式会社東芝
发明人： MORITA TAKEO , FUJIWARA KAZUMA
IPC分类号： G06F12/00 , G06F13/36 , G06F13/362
CPC分类号： G06F13/4243
摘要： PROBLEM TO BE SOLVED: To provide a data transfer system in which operation efficiency can be improved.SOLUTION: A data transfer system is provided which includes a bus having a plurality of lines each for transferring data at a first rate, respectively, a plurality of master devices connected to the bus, and a slave device connected to the bus. The slave device includes a plurality of slave interfaces which are connected to the bus and receive transfer instructions from the master devices via the bus at the first rate, respectively, an arbitration section which determines a processing order of transfer instructions received by the plurality of slave interfaces in accordance with priority information in which the plurality of master devices are prioritized in an order depending on relevance of processing contents among the plurality of master devices, and a processing section which performs data transfer processing with the outside in response to the transfer instructions at a second rate higher than the first rate in accordance with the processing order determined by the arbitration section.
摘要翻译：要解决的问题：提供可以提高运行效率的数据传送系统。解决方案：提供了一种数据传输系统，其包括具有多条线路的总线，每条线路分别用于以第一速率传送数据，连接到总线的多个主设备和连接到总线的从设备。从设备包括多个从接口，其分别连接到总线并经由总线以第一速率从主设备接收传送指令;仲裁部分，确定由多个从设备接收的传送指令的处理顺序根据多个主设备中的处理内容的相关性，按照与多个主设备中的处理内容的相关性的顺序来优先排列多个主设备的优先级信息的接口;以及处理部分，其响应于传输指令执行与外部的数据传送处理根据由仲裁部确定的处理顺序高于第一速率的第二速率。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2010152542A Memory system 审中-公开
标题翻译：记忆系统
公开(公告)号：JP2010152542A
公开(公告)日：2010-07-08
申请号：JP2008328465
申请日：2008-12-24
申请人： Toshiba Corp , Toshiba Information Systems (Japan) Corp , 東芝情報システム株式会社 , 株式会社東芝
发明人： MORITA TAKEO , AOKI AKIRA , MURAKAMI TETSUYA
IPC分类号： G06F12/16
CPC分类号： G11C7/02 , G06F11/073 , G06F11/076 , G06F11/1068 , G06F12/0246 , G06F2212/7209 , G11C7/1006
摘要： PROBLEM TO BE SOLVED: To provide a memory system for reducing the frequency of generation of an error as much as possible in performing access to a DRAM.
SOLUTION: A memory system includes: a first nonvolatile memory 2; a second volatile memory 4; and a transfer controller 3 for transferring data between a host device and the first memory 2 through the second memory 4. The transfer controller 3 includes error count means 14 and 15 for calculating a parity error in inputting/outputting data to each divided region for each division unit obtained by dividing the storage area of the second memory 4 into a plurality of regions, and for counting the number of times of accumulation of the parity error; and a means for making the divided region where the count value obtained by the error count means exceeds a prescribed number of times a use impossible state.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在执行对DRAM的访问时尽可能地减少错误产生的频率的存储器系统。解决方案：存储器系统包括：第一非易失性存储器2; 第二易失性存储器4; 以及用于通过第二存储器4在主机设备和第一存储器2之间传送数据的传送控制器3.传送控制器3包括差错计数装置14和15，用于计算每个分割区域的数据输入/输出中的奇偶校验错误通过将第二存储器4的存储区域划分为多个区域而获得的划分单元，并且用于对奇偶校验错误的累积次数进行计数; 以及用于使得由误差计数装置获得的计数值超过使用不可能状态的规定次数的分割区域的装置。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009087491A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2009087491A
公开(公告)日：2009-04-23
申请号：JP2007258002
申请日：2007-10-01
申请人： Toshiba Corp , Toshiba Information Systems (Japan) Corp , 東芝情報システム株式会社 , 株式会社東芝
发明人： MORITA TAKEO
IPC分类号： G11C29/42 , G11C16/06 , H03M13/35 , H04L1/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory in which efficient error correction can be performed and which has high reliability of read-write. SOLUTION: The semiconductor memory 1 has a memory part 2 and an error correction part 10, the error correction part 10 has a plurality of error correction circuits 11, 12 using correction codes of different systems, a recognition selecting circuit 14 recognizing occurrence tendency of errors detected by the error correction circuits 11, 12 and selecting one error correction circuit used for error correction from a plurality of error correction circuits 11, 12, a switching circuit 13 switching to the selected error correction circuit, and a memory circuit 15 storing information of the selected error correction circuit. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供可以执行有效的纠错并且具有高读取可靠性的半导体存储器。解决方案：半导体存储器1具有存储器部分2和纠错部分10，纠错部分10使用使用不同系统的校正码的多个纠错电路11,12，识别选择电路14识别出现由纠错电路11,12检测到的错误倾向，并从多个纠错电路11,12中选择一个用于纠错的纠错电路，切换到所选择的纠错电路的切换电路13以及存储电路15 存储所选择的纠错电路的信息。版权所有（C）2009，JPO＆INPIT

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