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1. 发明专利

JP2005183473A Circuit wiring board and manufacturing method therefor 有权
标题翻译：电路接线板及其制造方法
公开(公告)号：JP2005183473A
公开(公告)日：2005-07-07
申请号：JP2003418334
申请日：2003-12-16
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMADA HIROSHI , HIRAOKA TOSHIRO , HOTTA YASUYUKI , MATAKE SHIGERU , SAWANOBORI MISA
IPC分类号： H05K1/11 , H05K3/42
摘要： PROBLEM TO BE SOLVED: To provide a circuit wiring board having high resistance to curvature and shear distortion. SOLUTION: The circuit wiring board is provided with an insulator (11) having a porous structure, and conduction parts (12 and 13) formed by filling a hole in a partial region of the insulator with a conductive material. The conductive parts are formed of outer peripheral parts (12a and 13a) whose filling rate of the conductive material is high, and inner parts (12b and 13b) which are surrounded by the outer peripheral parts and have the low filling rate which changes stepwise. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有高抗曲率和剪切变形的电路布线板。解决方案：电路布线板设置有具有多孔结构的绝缘体（11）和通过用导电材料填充绝缘体的部分区域中的孔而形成的导电部件（12和13）。导电部分由导电材料的填充率高的外周部分（12a和13a）以及由外周部分包围且具有逐渐变化的低填充率的内部部分（12b和13b）形成。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005017301A Contact substrate for test of semiconductor device 审中-公开
标题翻译：用于半导体器件测试的接触衬底
公开(公告)号：JP2005017301A
公开(公告)日：2005-01-20
申请号：JP2004209023
申请日：2004-07-15
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAGUCHI NAOKO , SUGIZAKI YOSHIAKI , AOKI HIDEO , HIRAOKA TOSHIRO , HOTTA YASUYUKI , MATAKE SHIGERU , SAWANOBORI MISA
IPC分类号： G01R1/073 , G01R1/06 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a contact substrate for testing semiconductor device for conducting a test of an electronic component to be tested having fine electrode structure, while holding satisfactory electric contact.
SOLUTION: This contact substrate for testing semiconductor device is provided with the contact substrate 5 formed of an gas-permeable insulating material comprising either of a crystalline polymer containing a PTFE (polytetrafluoroethylene) and an aramid or a polyimide, having an upper face and an under face, and having a conductive via for connecting a space the upper face between the under face in its inside, and a deformation restraining part 41 for restraining thermal expansion of the contact substrate 5 to bring a thermal expansion coefficient as the whole contact substrate 5 into ±6 ppm/K or less with respect to a thermal expansion coefficient of the electronic component to be tested 1 connected electrically to the contact substrate 5.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于测试半导体器件的接触衬底，用于进行具有精细电极结构的待测电子元件的测试，同时保持令人满意的电接触。＆lt; P＆gt;解决方案：用于半导体器件测试的接触衬底设置有由透气绝缘材料形成的接触衬底5，该透气绝缘材料包括含有PTFE（聚四氟乙烯）和芳族聚酰胺或聚酰亚胺的结晶聚合物，其具有上表面并且具有用于连接其内表面的上表面的空间的导电通孔和用于抑制接触基板5的热膨胀以使热膨胀系数作为整体接触的变形抑制部41 基板5相对于与接触基板5电连接的待测电子部件1的热膨胀系数为±6ppm / K以下。（C）2005，JPO＆NCIPI

3. 发明专利

JP2004296504A Wiring member and its manufacturing method 有权
公开(公告)号：JP2004296504A
公开(公告)日：2004-10-21
申请号：JP2003083130
申请日：2003-03-25
申请人： Toshiba Corp , 株式会社東芝
发明人： HIRAOKA TOSHIRO , HOTTA YASUYUKI , MATAKE SHIGERU , SAWANOBORI MISA , YAMADA HIROSHI
IPC分类号： H05K1/02 , H01B5/14 , H01B13/00 , H01L23/14 , H01L23/15 , H01L23/498 , H05K1/03 , H05K3/10 , H05K3/12 , H05K3/38
CPC分类号： H01L23/49894 , H01L23/145 , H01L2924/0002 , H01L2924/3011 , H05K1/0306 , H05K1/0313 , H05K3/102 , H05K3/12 , H05K3/38 , H05K2201/0116 , H05K2201/0257 , H05K2201/2072 , Y10T428/24917 , Y10T428/249953 , Y10T428/249956 , Y10T428/249957 , Y10T428/249958 , Y10T428/249987 , Y10T428/249999 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wiring member that hardly causes the sinking, deviation, etc., of wiring at laminating time and has a continuity pattern having a sufficient film thickness. SOLUTION: This wiring member is provided with a sheet-like porous substrate (11) containing many three-dimensionally branched continuous pores having openings in the first and second main surfaces (11a and 11b) of the substrate (11), and a conductive section (12) which is formed on the first main surface (11a) of the porous substrate (11) and at least partially forms a mutually intruding structure (13) with the porous substrate (11) at the interface with the substrate (11). At least, either one of the mean diameter or mean opening ratio of the openings formed in the first main surface (11a) of the substrate (11) is smaller than that of the openings formed in the second main surface (11b) of the substrate (11). COPYRIGHT: (C)2005,JPO&NCIPI

4. 发明专利

JP2004285270A Composite member, method for manufacturing the same and material for forming the same 有权
公开(公告)号：JP2004285270A
公开(公告)日：2004-10-14
申请号：JP2003080846
申请日：2003-03-24
申请人： Toshiba Corp , 株式会社東芝
发明人： SAWANOBORI MISA , HIRAOKA TOSHIRO , HOTTA YASUYUKI , MATAKE SHIGERU
IPC分类号： C08L101/00 , C08K5/00 , C23C18/16 , H01B13/00 , H05K3/18
摘要： PROBLEM TO BE SOLVED: To form a conductive section precise and with good conductivity by plating treatment. SOLUTION: This method for manufacturing the composite member comprises: a step of forming an energy sensitive layer 3 composed of a material for forming the composite member on a surface of a substrate 1, a step of making a cation exchange radical and an anion exchange radical coexist in an area 3a in the energy sensitive layer in which the conductive section is formed by selectively supplying energy to the layer, a step of making a plating nuclei adsorbed on either the cation exchange radical or the anion exchange radical in the coexisting area of both kinds of the ion exchange radicals and a step of forming a conductive section 11 in the coexisting area by electroless plating. COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JP2006210622A Multilayer wiring board and semiconductor device 审中-公开
标题翻译：多层接线板和半导体器件
公开(公告)号：JP2006210622A
公开(公告)日：2006-08-10
申请号：JP2005020313
申请日：2005-01-27
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMADA HIROSHI , HOTTA YASUYUKI , MATAKE SHIGERU , SAWANOBORI MISA , HIRAOKA TOSHIRO
IPC分类号： H05K3/46
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To optimumly control a thermal expansion coefficient of an insulating layer of a semiconductor device where a semiconductor chip is mounted on a multilayer wiring board in which a circuit wiring layer and an insulating layer are alternately laminated on a core board. SOLUTION: The insulating layer is formed of porous materials 20 and 21 comprising holes 22 and 23 controlled in a constant direction. The circuit wiring layer is partially arranged in the porous material. In such region of the porous materials 20 and 21 where no circuit wiring is arranged, the insulating material of low thermal expansion coefficient is arranged. Thus, the multilayer wiring board and semiconductor device are easily realized in excellent flexibility and high connection reliability. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了最佳地控制半导体芯片的绝缘层的热膨胀系数，其中半导体芯片安装在电路布线层和绝缘层交替层叠在芯上的多层布线板上板。解决方案：绝缘层由多孔材料20和21形成，多孔材料20和21包括以恒定方向控制的孔22和23。电路布线层部分地布置在多孔材料中。在没有布置电路布线的多孔材料20和21的这种区域中，布置了低热膨胀系数的绝缘材料。因此，多层布线基板和半导体装置易于实现，具有优异的灵活性和高的连接可靠性。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2006100450A Porous wiring board 有权
标题翻译：多孔接线板
公开(公告)号：JP2006100450A
公开(公告)日：2006-04-13
申请号：JP2004282804
申请日：2004-09-28
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMADA HIROSHI , HIRAOKA TOSHIRO , HOTTA YASUYUKI , SAWANOBORI MISA , MATAKE SHIGERU , SAITO SATOSHI
IPC分类号： H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board capable of preventing shrinkage between wires to prevent a shift in designing position, improving connection reliability when making multiple layers, and obtaining sufficient conductivity. SOLUTION: The multilayer wiring board includes a sheetlike insulator (11) of a porous structure, an internal conductive part (12a) formed by filling pores of the sheetlike insulator with metal, and an external conductive part (12b) formed on the surface of the internal conductive part and connectable with the outside. A relation expressed by a formula (1) of 0.2≤(w 2 /w 1 )≤0.98 is observed between the maximum width (w 2 ) of the external conductive part parallel to a border surface of the sheetlike insulator and the maximum width (w 1 ) of the internal conductive part parallel to the border surface of the sheetlike insulator. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够防止电线之间收缩的多层布线板，以防止设计位置的偏移，提高制造多层时的连接可靠性，并获得足够的导电性。解决方案：多层布线板包括多孔结构的片状绝缘体（11），通过用金属填充片状绝缘体的孔而形成的内部导电部分（12a）和形成在其上的外部导电部分（12b）内部导电部分的表面并可与外部连接。在最大宽度（w 2 2 / W 1 ）≤0.98 >）和与片状绝缘体的边界表面平行的外部导电部分和与片状绝缘体的边界表面平行的内部导电部分的最大宽度（w 1 ）。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2005175127A Leadless chip carrier substrate and laminated package 有权
标题翻译：无铅芯片载体基板和层压包装
公开(公告)号：JP2005175127A
公开(公告)日：2005-06-30
申请号：JP2003411575
申请日：2003-12-10
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMADA HIROSHI , HIRAOKA TOSHIRO , HOTTA YASUYUKI , MATAKE SHIGERU , SAWANOBORI MISA
IPC分类号： H01L23/12 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a leadless chip carrier substrate, on the side face of which external electrodes having sufficiently high mechanical strength are formed. SOLUTION: The leadless chip carrier substrate is provided with a porous insulation substrate (3) and the external electrodes (2), including a conductive substance, formed on the side face of the porous insulation substrate. The conductive substance in the external electrodes (2) is integrated with the porous insulation substrate. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种无引线芯片载体基板，在其形成具有足够高的机械强度的外部电极的侧面上。解决方案：无引线芯片载体基板设置有形成在多孔绝缘基板的侧面上的多孔绝缘基板（3）和包括导电物质的外部电极（2）。外部电极（2）中的导电物质与多孔绝缘基板一体化。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2004039897A Method for connecting electronic device 审中-公开
公开(公告)号：JP2004039897A
公开(公告)日：2004-02-05
申请号：JP2002195690
申请日：2002-07-04
申请人： Toshiba Corp , 株式会社東芝
发明人： HIRAOKA TOSHIRO , ENDO MITSUYOSHI , YAMAGUCHI NAOKO , HOTTA YASUYUKI , MATAKE SHIGERU , AOKI HIDEO , SAWANOBORI MISA
IPC分类号： H01L23/12 , H01L21/60 , H01L21/68 , H01L23/538 , H05K1/18 , H05K3/18 , H05K3/42
CPC分类号： H01L24/24 , H01L21/568 , H01L21/6835 , H01L23/5389 , H01L24/82 , H01L24/96 , H01L2221/68359 , H01L2221/68363 , H01L2224/0231 , H01L2224/0401 , H01L2224/12105 , H01L2224/2413 , H01L2224/24137 , H01L2224/24195 , H01L2224/76155 , H01L2224/7665 , H01L2224/82039 , H01L2224/82102 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/19105 , H01L2924/3025 , H01L2924/351 , H05K1/185 , H05K3/185 , H05K3/422 , H05K2201/0116 , Y10T29/4913 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T29/4921 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for connecting an electronic device by which connection to an electronic device with a narrow pad pitch becomes possible, the displacement of positioning is hard to occur, and reworking can be applied. SOLUTION: The method includes a step where an electronic device 2 provided with at least one electrode 3 is placed on a sheet-like porous member 1 having a hole in its inside while the electrode is made close to the member 1, a step where an energy ray is selectively applied to form a latent image in an irradiation part or a non-irradiation part of the porous member 1, a step where the hole with the latent image of the porous member 1 is filled with a conductive substance to form conductive parts 5b and 6b, and a step where the porous member having the conductive part is integrally adhered to the electronic device. COPYRIGHT: (C)2004,JPO

9. 发明专利

JP2007304110A Contact substrate for semiconductor device test 审中-公开
标题翻译：用于半导体器件测试的接触衬底
公开(公告)号：JP2007304110A
公开(公告)日：2007-11-22
申请号：JP2007180289
申请日：2007-07-09
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAGUCHI NAOKO , SUGIZAKI YOSHIAKI , AOKI HIDEO , HIRAOKA TOSHIRO , HOTTA YASUYUKI , MATAKE SHIGERU , SAWANOBORI MISA
IPC分类号： G01R1/073 , G01R31/26 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To perform a test of an electronic component to be tested having a fine electrode structure while keeping satisfactory electric contact.
SOLUTION: This contact substrate includes a contact substrate 5 formed of a gas-permeable insulating material comprising either of liquid crystal polymer containing polytetrafluoroethylene and aramid or polyimide with 70% to 80% aperture ratio of a vacant hole, having an upper face and an under face, and having a plurality of conductive viae penetrating between the upper face and the under face in its inside, and adsorbing the electronic component to be tested 1 by air pressure, and a deformation restraining part 41 for restraining thermal expansion of the contact substrate 5 due to the difference between the thermal expansion coefficient of the electronic component to be tested 1 and the thermal expansion coefficient of the whole contact substrate 5, while the deformation restraining part 41 is projected and arranged from a plane which contacts with the electronic component to be tested so that the periphery of the plurality of the conductive viae may be surrounded.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：在保持令人满意的电接触的同时对具有精细电极结构的待测电子部件进行试验。该接触基板包括由透气绝缘材料形成的接触基板5，该导电绝缘材料包括含有聚四氟乙烯的液晶聚合物和芳族聚酰胺或具有70％至80％的空孔开口率的聚酰亚胺，其具有上表面和底面，并且在其内部具有穿过上表面和下表面之间的多个导电通孔，并且通过气压吸附待测试的电子部件1;以及变形抑制部41，用于抑制接触基板5由于待测电子部件1的热膨胀系数与整个接触基板5的热膨胀系数的差异，同时变形抑制部41从与电子部件接触的平面突出并配置待测试的部件，使得多个导电通孔的周边可以被包围。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2006196602A Method of manufacturing composite member and composite member forming material 有权
标题翻译：制备复合材料和复合材料成型材料的方法
公开(公告)号：JP2006196602A
公开(公告)日：2006-07-27
申请号：JP2005005432
申请日：2005-01-12
申请人： Toshiba Corp , 株式会社東芝
发明人： SAWANOBORI MISA , HOTTA YASUYUKI , MATAKE SHIGERU , YAMADA HIROSHI
IPC分类号： H05K3/18
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a composite member which is capable of stably forming a conductor layer micro pattern that is capable of preventing exposure light from scattering and hardly gets into a porous base material. SOLUTION: The method of manufacturing a composite member comprises a first process of forming a photosensitive layer inside the voids of the porous base material which is provided with continuous voids that are three-dimensionally formed, and filling the porous base material with a filler from either before or behind to form a composite member forming base material; a second process of subjecting the prescribed region of the composite member forming base material to pattern exposure from above the filling layer side; a third process of removing the filler; and a fourth process of selectively filling the exposed part or the unexposed part where the filler has been removed with a conductive material. The filler meets requirements represented by formula (1). In the formula (1), εA denotes the refractive index of the insulating material forming the porous base material, and εB is the refractive index of the filler. The refractive index of the air is one. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够稳定地形成能够防止曝光光散射并且难以进入多孔基材的导体层微图案的复合构件的制造方法。解决方案：制造复合构件的方法包括在多孔基材的空隙内形成感光层的第一工艺，该多孔基材具有三维形成的连续空隙，并将多孔基材填充到填料从之前或之后形成复合构件形成基材; 使形成基材的复合构件的规定区域从填充层侧上方进行图案曝光的第二工序; 第三种除去填料的方法; 以及选择性地填充已经用导电材料去除填料的暴露部分或未曝光部分的第四工序。填料符合式（1）所示的要求。在式（1）中，εA表示形成多孔基材的绝缘材料的折射率，εB是填料的折射率。空气的折射率是一。版权所有（C）2006，JPO＆NCIPI

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