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1. 发明专利

JP2012069695A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2012069695A
公开(公告)日：2012-04-05
申请号：JP2010212631
申请日：2010-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKURAI KATSUAKI , HOSONO KOJI
IPC分类号： H01L27/115 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device with a simplified structure.SOLUTION: A semiconductor storage device includes a plurality of memory cell units 3 provided over a substrate surface and including a plurality of memory cells connected in series. Each memory cell includes a semiconductor column 9, and a conductive film and an insulation film 5 around the semiconductor column 9, and stores data in a nonvolatile manner. The memory cell units form a plurality of blocks. A pipe layer PC includes a semiconductor layer connected to each semiconductor column of the first and second memory cell units adjacent to each other. A conductive plate BG is provided between each end of the first and second memory cell units and a surface of a semiconductor substrate, includes inside the pipe layers of at least two blocks, and controls conduction or non-conduction of the inside pipe layers. Supply path structures CBG1, LBG1, CBG2, TBG, and CBG3 are connected to the plate and supply to the plate the potential of a plate line DBG to be applied to the plate.
摘要翻译：要解决的问题：提供具有简化结构的半导体存储装置。解决方案：半导体存储装置包括设置在基板表面上并包括串联连接的多个存储单元的多个存储单元单元3。每个存储单元包括半导体柱9和半导体柱9周围的导电膜和绝缘膜5，并且以非易失性方式存储数据。存储单元单元形成多个块。管层PC包括连接到彼此相邻的第一和第二存储单元单元的每个半导体柱的半导体层。导电板BG设置在第一和第二存储单元单元的每一端和半导体衬底的表面之间，包括至少两个块的管层内，并且控制内管层的导通或非导通。供应路径结构CBG1，LBG1，CBG2，TBG和CBG3连接到板上，并向板提供板线DBG施加到板的电位。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2014049144A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2014049144A
公开(公告)日：2014-03-17
申请号：JP2012188530
申请日：2012-08-29
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKURAI KATSUAKI
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/08 , G11C11/4074 , G11C16/10 , G11C16/26 , G11C16/3427 , H01L27/1157 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To enhance the performance of a device by causing a voltage supplied to each wiring to reach a desired voltage early.SOLUTION: A semiconductor memory device includes a memory cell array that is configured by arranging memory cells; first wiring that is connected to the memory cells; and second wiring to which signals from the memory cells are supplied. A discharge circuit discharges a voltage of the first wiring by causing a first current to flow. In addition, a charging circuit charges the first wiring by causing a second current to flow. A control circuit controls the charging circuit by detecting the voltage of the first wiring. A current detection unit generates a third current that is proportional to the second current and determines the magnitude of the second current according to the magnitude of the third current. The discharging circuit is configured so as to be capable of controlling the magnitude of the first current according to a detection result of the current detection unit.
摘要翻译：要解决的问题：通过使提供给每个布线的电压提前达到期望的电压来提高器件的性能。解决方案：半导体存储器件包括通过布置存储器单元而配置的存储单元阵列; 连接到存储单元的第一布线; 以及提供来自存储单元的信号的第二布线。放电电路通过使第一电流流动来放电第一布线的电压。此外，充电电路通过使第二电流流动来对第一布线进行充电。控制电路通过检测第一布线的电压来控制充电电路。电流检测单元产生与第二电流成比例的第三电流，并根据第三电流的大小确定第二电流的大小。放电电路被配置为能够根据电流检测单元的检测结果来控制第一电流的大小。

3. 发明专利

JP2013200910A Semiconductor storage device and voltage output method of semiconductor storage device 审中-公开
标题翻译：半导体存储器件的半导体存储器件和电压输出方法
公开(公告)号：JP2013200910A
公开(公告)日：2013-10-03
申请号：JP2012067942
申请日：2012-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKURAI KATSUAKI , IWATA YOSHIHISA
IPC分类号： G11C16/06
CPC分类号： G11C5/147 , G11C16/30
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device that supplies an appropriate voltage to a non-selected source line SL without imparting temperature characteristics to a level-shifted voltage.SOLUTION: A semiconductor storage device comprises: a first comparator 100 using a first voltage and a second voltage as input voltage; a first capacitor 111 accumulating a potential of a first node; a current source 84 outputting first current to a second node; a resistance element 83 generating a third voltage at the second node; a second capacitor 112 accumulating a potential of the second node; first switches 103 and 104 that enable the first and second nodes respectively connected to the first and second capacitors to be commonly connected at a third node N62; and a second comparator 113 that defines a fourth voltage Vx obtained by charge-sharing with the first and second capacitors and a potential Vmon2 of a fourth node as input voltage, and matches the potential of the fourth node with a fourth voltage.
摘要翻译：要解决的问题：提供一种半导体存储装置，其向未选择的源极线SL提供适当的电压，而不对电平移位的电压赋予温度特性。解决方案：半导体存储装置包括：第一比较器100，电压和第二电压作为输入电压; 累积第一节点的电位的第一电容器111; 电流源84将第一电流输出到第二节点; 在第二节点处产生第三电压的电阻元件83; 累积第二节点的电位的第二电容器112; 第一开关103和104使得分别连接到第一和第二电容器的第一和第二节点在第三节点N62处共同连接; 以及第二比较器113，其限定通过与第一和第二电容器电荷共享获得的第四电压Vx和第四节点的电位Vmon2作为输入电压，并且将第四节点的电位与第四电压相匹配。

4. 发明专利

JP2012022742A Resistance change type memory 有权
标题翻译：电阻变化型存储器
公开(公告)号：JP2012022742A
公开(公告)日：2012-02-02
申请号：JP2010159098
申请日：2010-07-13
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMOSHITA MASAHIRO , SAKURAI KATSUAKI , SASAKI TAKAHIKO
IPC分类号： G11C13/00 , H01L27/10 , H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0092 , G11C2213/71 , G11C2213/72
摘要： PROBLEM TO BE SOLVED: To enhance the operation properties of a resistance change type memory.SOLUTION: A resistance change type memory according to an embodiment of the invention has a resistance change type memory element and a pulse generating circuit for generating a first pulse PLhaving an amplitude Vchanging the resistance state of the resistance change type memory element from high resistance state to the low resistance state, a third pulse PLhaving an third amplitude Vfor reading data with respect to the resistance change type memory element, and a fourth pulse having an amplitude Vbetween the amplitude Vand the amplitude V, a control circuit for controlling the operation of the resistance change type memory element and the pulse generating circuit. The control circuit provides the resistance change type memory element with the first pulse PLand then with the fourth pulse PL.
摘要翻译：要解决的问题：提高电阻变化型存储器的操作性能。解决方案：根据本发明的实施例的电阻变化型存储器具有电阻变化型存储元件和脉冲发生电路，用于产生具有第一脉冲的第一脉冲PL Set 将电阻变化型存储元件的电阻状态从高电阻状态改变为低电阻状态的振幅V 设定，第三脉冲PL Rd < / SB>具有用于相对于电阻变化型存储元件读取数据的第三幅度V Rd ，以及具有振幅V 的第四脉冲在振幅V 设定和振幅V Rd 之间的Dm ，控制电路的操作的控制电路改变型存储元件和脉冲发生电路。控制电路提供具有第一脉冲PL 设置的电阻变化型存储元件，然后用第四脉冲PL Dm 提供。版权所有（C）2012，JPO＆INPIT

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