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1. 发明专利

JP2017092687A 移動端末、輸送物監視システム、およびデータ送信制御方法有权
公开(公告)号：JP2017092687A
公开(公告)日：2017-05-25
申请号：JP2015219786
申请日：2015-11-09
申请人：株式会社東芝 , Toshiba Corp
发明人： MORI TOSHIKI , SAMEDA YOSHITOMI , NISHIKAWA HIROYUKI , INAMURA HIROYUKI , NANBA YOSHIKI , TANIGAWA TAKARYO
IPC分类号： H04M1/73 , H04M11/00 , H04W4/04 , H04W52/02
CPC分类号： Y02D70/00
摘要：【課題】消費電力を抑制することが可能な移動端末を提供する。【解決手段】一の実施形態によれば、移動端末は、輸送物の状態を周期的に測定する測定部と、測定部で測定された測定データを送信する送信部と、測定データを処理するデータ処理部と、を備える。データ処理部は、送信部が測定データを送信するたびに、当該測定データの送信の成否を判定する送信結果判定部と、測定データの送信が失敗した場合、当該失敗までの送信結果判定部の判定結果に応じて、送信部からの測定データの送信を一時的に休止させる制御部と、を備える。【選択図】図1

2. 发明专利

JP2013041403A Information processor and information processing method 有权
标题翻译：信息处理器和信息处理方法
公开(公告)号：JP2013041403A
公开(公告)日：2013-02-28
申请号：JP2011177628
申请日：2011-08-15
申请人： Toshiba Corp , 株式会社東芝
发明人： NANBA YOSHIKI , YAMAMOTO TAKAHARU , TASHIRO TAICHI , NISHIKAWA HIROYUKI , NAKAMURA KOTA
IPC分类号： G06F3/06 , G06F12/00 , G06F13/10
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0688
摘要： PROBLEM TO BE SOLVED: To provide an information processor capable of using a general-purpose storage device for real time control.SOLUTION: The information processor comprises: a state table; a monitoring part; a buffer memory; a timer; a data processing part; and a responding part. The monitoring part monitors the operation state of the storage device and sets the operation state of the storage device as a monitoring result to the state table. When a data-writing is requested from the host device, the responding part instructs the timer to start counting and sets a data-writing destination to the state table; and instructs the data-writing to the storage device for writing. Then, the part causes data for writing, which is sent from the host device for within a certain period of time, to be held in the buffer memory; and when receiving notification that time is up from the timer, it returns a response, which indicates completion of the writing for the write request, to the host device.
摘要翻译：要解决的问题：提供能够使用通用存储设备进行实时控制的信息处理器。解决方案：信息处理器包括：状态表; 监控部分; 缓冲存储器一个计时器数据处理部分; 和响应部分。监视部分监视存储装置的操作状态，并将存储装置的操作状态设置为状态表的监视结果。当从主机设备请求数据写入时，响应部分指示定时器开始计数并将数据写入目的地设置为状态表; 并指示对存储装置进行写入的数据写入。然后，该部分使得在一定时间内从主机设备发送的写入数据被保存在缓冲存储器中; 并且当从定时器接收到该时间到达的通知时，它向主机设备返回一个响应，该响应指示写入请求的写入完成。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2008134838A Bus device 审中-公开
标题翻译：总线设备
公开(公告)号：JP2008134838A
公开(公告)日：2008-06-12
申请号：JP2006320667
申请日：2006-11-28
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKATANI HIROSHI , TAKENE KOICHI , NISHIKAWA HIROYUKI , KAWAMURA TOSHIKAZU , SAWADA AKIRA , SAMEDA YOSHITOMI , OKABE MOTOHIKO
IPC分类号： G06F13/00 , G06F11/30
摘要： PROBLEM TO BE SOLVED: To facilitate accurate fault analysis on the occurrence of a fault in a bus device or an external bus. SOLUTION: A bus device 10a, connected to both an internal bus 30 and an external bus 20, includes a local register 14 for storing first data, an internal bus controller 11, a bus configuration register 15 for storing second data, a bus interface controller 13, and a data transfer controller 12. The bus device also includes a data collector 16 for collecting from the internal bus controller at least one of the access history of the internal bus controller to the internal bus, the input/output history of the first data to the local register and the input/output history of the second data to the bus configuration register, collecting from the bus interface controller the access history of the bus interface controller to the external bus and the input/output history of the second data to the bus configuration register, and then extracting the history data and outputting it to an external memory unit through the internal bus. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了便于对总线设备或外部总线故障发生的准确故障分析。
解决方案：连接到内部总线30和外部总线20两者的总线装置10a包括用于存储第一数据的本地寄存器14，内部总线控制器11，用于存储第二数据的总线配置寄存器15 总线接口控制器13和数据传输控制器12.总线装置还包括数据收集器16，用于从内部总线控制器收集内部总线控制器的访问历史中的至少一个到内部总线，输入/输出历史将第一个数据发送到本地寄存器，将第二个数据的输入/输出历史记录到总线配置寄存器，从总线接口控制器收集总线接口控制器的访问历史到外部总线以及输入/输出历史第二数据发送到总线配置寄存器，然后提取历史数据并通过内部总线将其输出到外部存储器单元。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2014014212A Monitoring controller 审中-公开
标题翻译：监控控制器
公开(公告)号：JP2014014212A
公开(公告)日：2014-01-23
申请号：JP2012150016
申请日：2012-07-03
申请人： Toshiba Corp , 株式会社東芝
发明人： MARUCHI SHUNYA , SAMEDA YOSHITOMI , INAMURA HIROYUKI , TAKEHARA JUN , NISHIKAWA HIROYUKI , YOSHIKAWA MASAOMI , NANBA YOSHIKI , ONISHI NAOYA
IPC分类号： H02J13/00
摘要： PROBLEM TO BE SOLVED: To provide a monitoring controller capable of making effective use of electric power charged into storage batteries.SOLUTION: The monitoring controller includes a communication section and an arithmetic section. The communication section acquires a discharge signal from a system that commands discharges of storage batteries installed on a power system in a jurisdiction. The arithmetic section acquires the priority of voltage conversion sections each converting a DC voltage of the storage battery from a characteristic information database when the communication section acquires the discharge signal. Moreover, the communication section outputs a control signal for discharging the storage battery connected with the voltage conversion section in the order of the voltage conversion sections with higher priority.
摘要翻译：要解决的问题：提供能够有效利用充电到蓄电池中的电力的监视控制器。解决方案：监视控制器包括通信部分和运算部分。通信部从控制管理区域的电力系统的蓄电池的放电指令的系统取得放电信号。运算部从通信部获取放电信号时，从特性信息数据库获取各自转换蓄电池的直流电压的电压转换部的优先级。此外，通信部分输出用于以与电压转换部分连接的蓄电池放电的控制信号按照电压转换部分的优先次序排列。

5. 发明专利

JP2008282178A Industrial controller 审中-公开
标题翻译：工业控制器
公开(公告)号：JP2008282178A
公开(公告)日：2008-11-20
申请号：JP2007125065
申请日：2007-05-09
申请人： Toshiba Corp , 株式会社東芝
发明人： SAMEDA YOSHITOMI , NAKATANI HIROSHI , SAWADA AKIRA , TAKEHARA JUN , NISHIKAWA HIROYUKI , OKABE MOTOHIKO
IPC分类号： G06F11/14
CPC分类号： H04L9/008 , G06F11/085
摘要： PROBLEM TO BE SOLVED: To provide an industrial controller for detecting and correcting any bit error in the case of the arithmetic operation of numeric data in response to every arithmetic command in a real time with simple configurations by an industrial controller. SOLUTION: In this industrial controller, a first arithmetic operating part 11 is provided with a first modular arithmetic code generation part 11b for encoding numeric data transmitted by a command output from a central controller 31; a first arithmetic operation processor 11a for executing an operation instruction based on a command from the central controller 13 by using encoded numerical data (modular arithmetic code) as an input operand, and for outputting it in the form of a modular arithmetic code; and a first modular arithmetic code decoder 11c for deciding the presence/absence of the bit error of the output data of the first arithmetic operation processor, and for, when any bit error is detected, correcting the detected bit error, and for outputting the decoded numeric data. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种工业控制器，用于在工业控制器的简单配置下，响应于实时的每个算术命令在数值数据的算术运算的情况下检测和校正任何位错误。解决方案：在这个工业控制器中，第一算术运算部分11设有第一模运算代码生成部分11b，用于编码由中央控制器31输出的命令发送的数字数据; 第一算术运算处理器11a，用于通过使用编码数字数据（模数算术代码）作为输入操作数，基于来自中央控制器13的命令执行操作指令，并以模数算术代码的形式输出; 以及用于判定第一算术运算处理器的输出数据的位错误的存在/不存在的第一模算术码解码器11c，并且当检测到任何位错误时，校正检测到的位错误，并且用于输出解码的数字数据。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2005341754A Power converter and superconducting power storage uint 有权
标题翻译：电源转换器和超级电源存储UINT
公开(公告)号：JP2005341754A
公开(公告)日：2005-12-08
申请号：JP2004159567
申请日：2004-05-28
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIGETA MASAAKI , NISHIKAWA HIROYUKI , IOKA SHIGERU , SENDA IKUO , SHINOHARA HIROFUMI
IPC分类号： H02M7/48 , H02M7/483
摘要： PROBLEM TO BE SOLVED: To provide a power converter and a superconducting power storage unit having a simple and high performance control system in which the dimensions, weight, capacity and cost of an SMES coil, a cooler and a main circuit can be reduced sharply. SOLUTION: The power converter comprising capacitors, connected with the output end of a plurality of unit converters connected with a current source, while being interconnected in series, a transformer connecting the capacitor and a power supply system; a voltage detector for detecting the line voltage of the power supply system; a voltage detector for detecting the voltage of the capacitor, a current detector for detecting the current of the power supply system; and a controller performing feedforward control by the detection values of the system current, when instantaneous voltage drop occurs in the power supply system and performing capacitor voltage feedback control so that the capacitor voltage vector amplitude and the system phase voltage vector phase, immediately before instantaneous voltage drop have a capacitor voltage amplitude command value and a voltage phase command value, respectively, is provided with an instantaneous voltage drop compensation control function for supplying a required power to a load stably, during the instantaneous voltage drop in the power supply system. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有简单和高性能控制系统的功率转换器和超导电力存储单元，其中SMES线圈，冷却器和主电路的尺寸，重量，容量和成本可以是急剧下降解决方案：包括电容器的功率转换器，其与串联连接的多个与电流源连接的单元转换器的输出端连接，连接电容器和电源系统的变压器; 电压检测器，用于检测电源系统的线路电压; 电压检测器，用于检测电容器的电压;电流检测器，用于检测电源系统的电流; 并且控制器通过系统电流的检测值进行前馈控制，当电源系统中发生瞬时电压降并执行电容器电压反馈控制使得电容器电压矢量幅度和系统相位电压矢量相位在瞬时电压之前分别具有电容器电压幅度指令值和电压相位指令值的瞬时电压降补偿控制功能，用于在电源系统的瞬时电压降期间稳定地向负载提供所需电力。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2011188376A Image processing apparatus and image processing method 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：JP2011188376A
公开(公告)日：2011-09-22
申请号：JP2010053597
申请日：2010-03-10
申请人： Toshiba Corp , 株式会社東芝
发明人： KIMIYAMA KENJI , BABA KENJI , NISHIKAWA HIROYUKI , KAWAMURA TOSHIKAZU
IPC分类号： H04N7/01
摘要： PROBLEM TO BE SOLVED: To provide an image processing apparatus capable of generating an enlarged progressive video image by improving a resolution with high image quality while utilizing a super resolution system. SOLUTION: The invention relates to an image processing apparatus 10 including an IP conversion processing unit 11 and an enlargement processing unit 13 of a super resolution system. The IP conversion processing unit 11 converts an interlaced video image into a progressive video image. The enlargement processing unit 13 performs super resolution processing and uses the motion vector information 120 of a plurality of frames constituting the progressive video image and an interlaced video image 100 to generate an enlarged progressive video image 130. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够通过在利用超分辨率系统的同时提高具有高图像质量的分辨率来生成放大的逐行视频图像的图像处理装置。解决方案：本发明涉及一种包括超分辨率系统的IP转换处理单元11和放大处理单元13的图像处理设备10。 IP转换处理单元11将隔行视频图像转换成逐行视频图像。放大处理单元13执行超分辨率处理，并且使用构成逐行视频图像的多个帧的运动矢量信息120和隔行扫描视频图像100来生成放大的逐行视频图像130.版权所有（C）2011 ，JPO＆INPIT

8. 发明专利

JP2011061603A Image processing device, and method for processing image 有权
标题翻译：图像处理装置，以及处理图像的方法
公开(公告)号：JP2011061603A
公开(公告)日：2011-03-24
申请号：JP2009210554
申请日：2009-09-11
申请人： Toshiba Corp , 株式会社東芝
发明人： KIMIYAMA KENJI , NISHIKAWA HIROYUKI , YOSHIKAWA MASAOMI , NISHIMURA NOBUTAKA
IPC分类号： H04N1/21 , G06F12/02 , G06T1/60 , H04N1/387
摘要： PROBLEM TO BE SOLVED: To provide an image processing device which can reduce the number of times of access to an image memory, and to provide a method for processing an image.
SOLUTION: A configuration in which an image data processing section 33 that has been mounted in an image processing unit 10 is mounted in an image memory controller 30 and additionally, an address conversion section 32 and a control section 31 are mounted is used. Moreover, by defining a virtual readout address area of an image memory 20, a memory usage can be reduced and the number of times of access to a memory can be reduced. Communication speed can be improved.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以减少对图像存储器的访问次数的图像处理装置，并且提供一种用于处理图像的方法。解决方案：其中已经安装在图像处理单元10中的图像数据处理部分33安装在图像存储器控制器30中并且另外安装地址转换部分32和控制部分31的配置被使用。此外，通过定义图像存储器20的虚拟读出地址区域，可以减少存储器使用，并且可以减少对存储器的存取次数。通信速度可以提高。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2011061438A Image processor 有权
标题翻译：图像处理器
公开(公告)号：JP2011061438A
公开(公告)日：2011-03-24
申请号：JP2009208264
申请日：2009-09-09
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKAI EIGO , SAMEDA YOSHITOMI , YOSHIKAWA MASAOMI , NISHIKAWA HIROYUKI
IPC分类号： H04N7/18 , G06T1/00 , G06T1/20 , H04N7/173
摘要： PROBLEM TO BE SOLVED: To provide an image processor which scalably changes imaging points. SOLUTION: Image data obtained from a plurality of imaging apparatuses 20-1 to 20-n are temporarily held in a plurality of FIFOs 112-1 to 112-n constructed on an FPGA. A register part 114 receives synchronizing signals from the imaging apparatuses 20-1 to 20-n. On receipt of the synchronizing signal from the imaging apparatus that has started imaging last, the register part 114 outputs an output start signal to a control part 115. The control part 115 outputs the image data in a predetermined order from the FIFOs 112-1 to 112-n when the output start signal is received. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供可以成像点变化的图像处理器。解决方案：从多个成像设备20-1至20-n获得的图像数据暂时保存在FPGA上构成的多个FIFO 112-1至112-n中。寄存器部分114接收来自成像设备20-1至20-n的同步信号。在从最初开始成像的成像装置接收到同步信号的情况下，寄存器部分114将输出开始信号输出到控制部分115.控制部分115以预定顺序从FIFO 112-1输出图像数据 112-n，当接收到输出开始信号时。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2011060137A Image processing apparatus and method 有权
标题翻译：图像处理装置和方法
公开(公告)号：JP2011060137A
公开(公告)日：2011-03-24
申请号：JP2009210915
申请日：2009-09-11
申请人： Toshiba Corp , 株式会社東芝
发明人： YOSHIKAWA MASAOMI , FUKAI EIGO , NISHIKAWA HIROYUKI , SAMEDA YOSHITOMI
IPC分类号： G06T1/20 , H03K19/173
摘要： PROBLEM TO BE SOLVED: To provide an image processing apparatus and method, capable of controlling a plurality of image memories with one memory access controller, and minimizing the scale of an interface.
SOLUTION: The memory access controller 30 includes an input unit N1 for receiving image data from a function 1 and for input of the image data, and a plurality of output units OUT1, OUT2, ..., OUTn corresponding to a plurality of functions 1, 2, ..., n, respectively, and upon receiving a transmission request for image data from the function 2, reads image data from one memory among memories 1, 2, ..., n to output the image data to the function 2 from which the transmission request is received through the output unit OUT2.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够利用一个存储器访问控制器来控制多个图像存储器并且使接口的规模最小化的图像处理装置和方法。存储器访问控制器30包括用于从功能1接收图像数据并输入图像数据的输入单元N1以及对应于多个图像数据的多个输出单元OUT1，OUT2，...，OUTn 功能1，2，...，n，并且在从功能2接收到对图像数据的发送请求时，从存储器1,2，...，n中的一个存储器读取图像数据，以输出图像数据到通过输出单元OUT2接收到发送请求的功能2。版权所有（C）2011，JPO＆INPIT

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