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1. 发明专利

JP2004063667A Semiconductor device having capacitor formed in multi-layer wiring layer 有权
公开(公告)号：JP2004063667A
公开(公告)日：2004-02-26
申请号：JP2002218399
申请日：2002-07-26
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA TAKESHI , MIYAMOTO KOJI , NAKAJIMA YUICHI
IPC分类号： H01L21/768 , H01L21/02 , H01L21/822 , H01L21/8234 , H01L23/522 , H01L27/04 , H01L27/06 , H01L27/088
CPC分类号： H01L28/40 , H01L21/76838 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a capacitor formed in a multi-layer wiring layer for preventing the generation of the short-circuit of the upper electrode of a capacitor and wiring and the capacitor embedded in an inter-layer insulating film, or the excessive etching of a via bottom at the time of forming via/wiring on the capacitor with high reliability. SOLUTION: A thick via 51 is formed on the upper face of an upper electrode 35 of a capacitor formed in a predetermined wiring layer, and a via 60a thinner than the thick via 51 and copper wiring 61a arranged in a wiring layer formed at the upper part of the predetermined wiring layer are successively formed through the diffusion stopper film of copper at the upper part of the via 51. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2005019452A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005019452A
公开(公告)日：2005-01-20
申请号：JP2003178237
申请日：2003-06-23
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA TAKESHI , USUI TAKAKIMI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L23/367 , H01L23/485 , H01L27/04 , H01L29/417
CPC分类号： H01L24/05 , H01L23/367 , H01L23/3677 , H01L29/41725 , H01L2224/02166 , H01L2224/05093 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01055 , H01L2924/01074 , H01L2924/04953 , H01L2924/1306 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that also protects a wiring layer used in the surge current route of an ESD protective circuit by efficiently radiating the heat generated in the wiring layer. SOLUTION: This semiconductor device is provided with: an input protective circuit having a protective element which is connected to the wiring between an external terminal and an internal circuit, and protects the internal circuit from excessive electrostatic surge inputs impressed upon the external terminal; a first metallic wiring layer 25 connected to the input protective circuit and contained in the surge current route; and a radiator 20 connected to the first metallic wiring layer 25 and constituted by using wiring made of a material having good thermal conductivity. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件，其还通过有效地辐射在布线层中产生的热量来保护用于ESD保护电路的浪涌电流路径中的布线层。解决方案：该半导体器件具有：输入保护电路，其具有与外部端子和内部电路之间的布线连接的保护元件，并且保护内部电路免受外部端子上施加的过多静电浪涌输入 ; 连接到输入保护电路并包含在浪涌电流路径中的第一金属布线层25; 以及连接到第一金属布线层25并由使用由具有良好导热性的材料制成的布线构成的散热器20。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2009105149A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009105149A
公开(公告)日：2009-05-14
申请号：JP2007274071
申请日：2007-10-22
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA TAKESHI
IPC分类号： H01L21/8242 , H01L21/768 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of forming a capacitor having sufficient capacity without affecting processes and characteristics when a DRAM is mixedly mounted on an SoC.
SOLUTION: The semiconductor device includes: a transistor region which is formed on a semiconductor substrate 11 and element-separated, a first interlayer film 19 formed on the semiconductor substrate 11; first and second contact plugs 20 and 21 which are formed on the first interlayer film 19 and connected to the transistor region respectively; a first capacitor which is formed in the first contact plug 20 and has an MIM structure being composed of an electrode layer 22a, an insulating layer 22b and a Cu layer 22c; and a bit line 29 connected to the second contact plug 21.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够形成具有足够容量的电容器的半导体器件，而不会在将DRAM混合安装在SoC上时影响工艺和特性。解决方案：半导体器件包括：形成在半导体衬底11上并且元件分离的晶体管区域，形成在半导体衬底11上的第一层间膜19; 第一和第二接触插塞20和21，其形成在第一层间膜19上并分别连接到晶体管区域; 形成在第一接触插塞20中并具有由电极层22a，绝缘层22b和Cu层22c组成的MIM结构的第一电容器; 和连接到第二接触插头21的位线29。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JPH06196641A WELL REGION IN SEMICONDUCTOR SUBSTRATE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06196641A
公开(公告)日：1994-07-15
申请号：JP34366292
申请日：1992-12-24
申请人： TOSHIBA CORP
发明人： MATSUNAGA TAKESHI
IPC分类号： H01L21/8238 , H01L27/092
摘要： PURPOSE:To form a high-concentration region only in the deep part of a substrate without the fluctuation of the surface concentration of the substrate when well layers having the different conducting types from the substrate are formed at the deep part of the surface of the substrate. CONSTITUTION:A P-type silicon substrate 11 is etched, and an N-type well layer 16 is formed at the deep part. An oxide film 14-2 is formed so that the film is surrounded with the N-type well layer 16 at the side surface of the N-type well layer in the depth direction. A silicon epitaxial layer 17 having the same conducting type and the same concentration as those of the substrate is formed at the upper part of the N-type well layer 16. A P-type well layer 23-1 and an N-type well layer 24-1 are formed at the surface of the epitaxial layer 17. Meanwhile, a P-type well layer 23-2 and an N-type well layer 24-2 are formed at the surface of the substrate 11 at the outer part of the N-type well layer 16. An oxide film 18 is formed on the substrate 11, where the well layers are formed.

5. 发明专利

JPH0634587A EVALUATION APPARATUS AND METHOD FOR SEMICONDUCTOR MANUFACTURING APPARATUS 失效
公开(公告)号：JPH0634587A
公开(公告)日：1994-02-08
申请号：JP8959092
申请日：1992-03-14
申请人： TOSHIBA CORP
发明人： NORISHIMA MASAYUKI , MATSUNAGA TAKESHI , TOYOSHIMA YOSHIAKI
IPC分类号： G01N27/04 , G01M11/00 , G01M11/02 , G01R1/067 , G03F7/20 , G03F7/207 , H01L21/027 , H01L21/30 , H01L21/66
摘要： PURPOSE:To obtain an evaluation apparatus and method of a semiconductor manufacturing apparatus for evaluating characteristics of an aligner by a method where a photoresist is exposed through a photomask mounted on an & to form a conducting film on a semiconductor substrate and a resistance value thereof is measured. CONSTITUTION:A photomask as illustrated shows a mask pattern of a reticle which is used in an aligner such as stepper and projected into an exposure area 32. The mask pattern comprises a plurality of blocks (subchips) 31 equal in the shape of patterns and the respective blocks 31 have a plurality of resistance measuring patterns and sheet resistance measuring patterns as required. The blocks 31 are arranged within the reticle and resistance chant of the blocks 31 are compared to evaluate a lens of the aligner.

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