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1. 发明专利

JP2011018755A Nonvolatile semiconductor storage device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2011018755A
公开(公告)日：2011-01-27
申请号：JP2009161982
申请日：2009-07-08
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWADA NOBUHITO , NISHIHARA KIYOHITO
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which can be improved in integration and reduced in cost, and to provide a method of manufacturing the same.SOLUTION: The nonvolatile semiconductor storage device includes a semiconductor substrate 10 including a plurality of diffusion layers, a first memory film 15 formed on the semiconductor substrate, a plurality of first gate electrodes WL1 and a first selection gate electrode SG1 formed on the first memory film, a second memory film 24 formed on the plurality of first gate electrodes and the first selection gate electrode, a first semiconductor layer 25 formed on the second memory film, a third memory film 30 formed on the first semiconductor layer, and a plurality of second gate electrodes and a second selection gate electrode SG2 formed on the third memory film.
摘要翻译：要解决的问题：提供可以提高集成度和降低成本的非易失性半导体存储装置，并提供其制造方法。解决方案：非易失性半导体存储装置包括：半导体衬底10，包括多个扩散形成在半导体衬底上的第一存储膜15，形成在第一存储膜上的多个第一栅电极WL1和第一选择栅电极SG1，形成在多个第一栅电极上的第二存储膜24和第一存储膜选择栅电极，形成在第二存储膜上的第一半导体层25，形成在第一半导体层上的第三存储膜30，以及形成在第三存储膜上的多个第二栅电极和第二选择栅电极SG2。

2. 发明专利

JP2011003742A Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2011003742A
公开(公告)日：2011-01-06
申请号：JP2009145764
申请日：2009-06-18
申请人： Toshiba Corp , 株式会社東芝
发明人： NAGASHIMA MASASHI , KAWADA NOBUHITO
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1211 , H01L27/11568 , H01L27/11578 , H01L29/4234 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To laminate a memory cell longitudinally while improving controllability of drain current, and to lower difficulty in processing a control gate electrode and a charge storage layer even when a fin structure is used for the memory cells.SOLUTION: A nonvolatile semiconductor memory device is provided with a body layer 17 having a channel area embedded in a fin control gate electrode 12a with a block layer 13, the charge storage layer 14 and a tunnel oxide film 15 interposed sequentially.
摘要翻译：要解决的问题：即使在使用翅片结构用于存储单元时，也可以纵向层叠存储单元，同时提高漏极电流的可控性，并且降低处理控制栅电极和电荷存储层的困难。解决方案：非易失性半导体存储器件具有主体层17，其主体层17具有嵌入在翅片控制栅极电极12a中的通道区域，其具有顺序插入的阻挡层13，电荷存储层14和隧道氧化物膜15。

3. 发明专利

JP2009164271A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009164271A
公开(公告)日：2009-07-23
申请号：JP2007340663
申请日：2007-12-28
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWADA NOBUHITO , AKAHORI HIROSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a technique which can prevent an electric field concentration due to birds beaks and can suppress demerits of the birds beaks. SOLUTION: This invention relates to a semiconductor device having bit lines and word lines, characterized by comprising: a substrate in which there are provided plural first trenches extending in the bit-line direction and there are formed the birds beaks at upper edges of side surfaces constituting sidewalls of the first trenches; a first gate insulating film formed on the substrate between the first trenches; a floating gate formed on the first gate insulating film between the first trenches and located between second trenches extending in the word-line direction, wherein any birds beaks are not formed at lower edges of the side surfaces facing sides of the first trenches; a second gate insulating film formed on the floating gate between the second trenches; and a control gate formed on the second gate insulating film between the second trenches. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以防止由于鸟类喙引起的电场浓度并且可以抑制鸟喙的缺点的技术。解决方案：本发明涉及具有位线和字线的半导体器件，其特征在于包括：衬底，其中设置有沿位线方向延伸的多个第一沟槽，并且在上边缘处形成鸟嘴的侧表面构成第一沟槽的侧壁; 在所述第一沟槽之间的所述基板上形成的第一栅极绝缘膜; 形成在所述第一沟槽之间的所述第一栅极绝缘膜上并且位于沿所述字线方向延伸的第二沟槽之间的浮置栅极，其中在所述第一沟槽的侧面的侧面的下边缘处不形成任何鸟嘴; 形成在所述第二沟槽之间的所述浮动栅极上的第二栅极绝缘膜; 以及形成在第二沟槽之间的第二栅极绝缘膜上的控制栅极。版权所有（C）2009，JPO＆INPIT

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