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1. 发明专利

JP2005175299A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005175299A
公开(公告)日：2005-06-30
申请号：JP2003415319
申请日：2003-12-12
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO HITOSHI
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/78
CPC分类号： H01L29/66628 , H01L21/76224 , H01L21/823481
摘要： PROBLEM TO BE SOLVED: To suppress growth of the facet of an epitaxial silicon film formed on a source region and a drain region.
SOLUTION: The semiconductor device has the epitaxial silicon film 118 formed on the source region 101 and drain region 101 by using epitaxial growth. The surface height of an element separation insulating film 102 which comes into contact with the source region 101 and drain region 101 is equalized to or less than the surface height of a semiconductor substrate 100 where the source region 101 and drain region 101 are formed, and a stopper 116 is formed of a material (e.g. SiN) different from the element separation insulating film 102 on a portion on the element separation insulating film 102.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：抑制形成在源极区域和漏极区域上的外延硅膜的面的生长。解决方案：半导体器件具有通过外延生长在源极区101和漏极区101上形成的外延硅膜118。与源极区域101和漏极区域101接触的元件分离绝缘膜102的表面高度等于或小于形成源极区域101和漏极区域101的半导体衬底100的表面高度，以及止动件116由元件隔离绝缘膜102上的一部分上与元件隔离绝缘膜102不同的材料（例如SiN）形成。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2004029461A Photomask, exposing method and manufacturing method of semiconductor device 审中-公开
公开(公告)号：JP2004029461A
公开(公告)日：2004-01-29
申请号：JP2002186665
申请日：2002-06-26
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO HITOSHI
IPC分类号： G03F1/68 , G03F1/70 , G03F7/20 , H01L21/027 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To provide a photomask by which throughput of a multiple exposure process can be improved, administrative cost can be reduced and area can be utilized effectively. SOLUTION: The photomask comprises a light transmissive substrate 11, first mask patterns 15 arranged on a first surface of the light transmissive substrate 11 and second mask patterns 17 arranged on a second surface of the light transmissive substrate 11 facing the first mask patterns 15. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2007281300A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007281300A
公开(公告)日：2007-10-25
申请号：JP2006107833
申请日：2006-04-10
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO HITOSHI , TAKASU YASUO
IPC分类号： H01L21/76
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has an element separation insulating film of a good characteristic even a groove of a high aspect ratio.
SOLUTION: The semiconductor device includes a semiconductor substrate (1) which is formed on the surface and has a groove to divide an element area. A first insulating film (11) having a first density is located in the groove. A second insulating film (12) is located on the first insulating film in the groove, and has a density higher than the first density. A third insulating film (4) composed of a material different from those of the first insulating film or an air gap (31) is formed between the first insulating film and the side of the groove, and reaches at least the interface between the first insulating film and the second insulating film. The groove is filled with the first insulating film and the second insulating film.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种具有甚至具有高纵横比的槽的良好特性的元件隔离绝缘膜的半导体器件。解决方案：半导体器件包括形成在表面上并具有用于划分元件区域的凹槽的半导体衬底（1）。具有第一密度的第一绝缘膜（11）位于槽中。第二绝缘膜（12）位于沟槽中的第一绝缘膜上，并且具有高于第一密度的密度。在第一绝缘膜和槽的侧面之间形成由与第一绝缘膜或气隙（31）不同的材料构成的第三绝缘膜（4），并且至少达到第一绝缘膜薄膜和第二绝缘膜。凹槽填充有第一绝缘膜和第二绝缘膜。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2005055815A Photomask, method for forming pattern and method for manufacturing semiconductor device 审中-公开
标题翻译：光刻胶，形成图案的方法和制造半导体器件的方法
公开(公告)号：JP2005055815A
公开(公告)日：2005-03-03
申请号：JP2003289008
申请日：2003-08-07
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO HITOSHI
IPC分类号： G03C5/00 , G03F1/54 , G03F1/56 , G03F7/16 , G03F7/20 , G03F9/00 , G03G16/00 , H01L21/00 , H01L21/027 , G03F1/08
CPC分类号： G03F1/70
摘要： PROBLEM TO BE SOLVED: To provide a photomask capable of transferring an appropriate mask pattern to the objective film where a systematic level difference is formed.
SOLUTION: The photomask comprises: a transparent substrate 70; a first mask pattern 84 disposed in a certain region on the transparent substrate 70; a second mask pattern 86 disposed in a region different from the above region on the transparent substrate 70; and a light transmitting film 88 disposed on the first mask pattern 84 and having the optical film thickness which deepens the focus position of the first mask pattern 84 than the second mask pattern 86.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够将适当的掩模图案转印到形成系统水平差的目标膜的光掩模。光掩模包括：透明基板70; 设置在透明基板70上的一定区域中的第一掩模图案84; 第二掩模图案86，设置在与透明基板70上的上述区域不同的区域中; 以及设置在第一掩模图案84上并且具有加深第一掩模图案84的聚焦位置的光学膜厚度的透光膜88比第二掩模图案86.版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2004101537A Nuclear reactor output measuring apparatus 审中-公开
公开(公告)号：JP2004101537A
公开(公告)日：2004-04-02
申请号：JP2003394069
申请日：2003-11-25
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI RYOICHI , ODA TADAYOSHI , ITO HITOSHI
IPC分类号： G21C17/108 , G01T1/12 , G21C17/10
摘要： PROBLEM TO BE SOLVED: To reduce influences of a failure as much as possible by enabling continuation of other processings without stopping a processing, even if part of gammer-ray thermometers fail. SOLUTION: A nuclear reactor output measuring apparatus converts each of output signals from a plurality of the gamma-ray thermometers 84 installed in a reactor 81 into a quantity of generated heat by a conversion formula and calculates a peripheral fuel rods output distribution by correcting an output distribution calculation value, by using the quantity of generated heat. The apparatus comprises quantity-of-generated-heat conversion sections 3, 4 and 5, respectively provided in regions for converting the outputs of the thermometers into the quantities of generated heat, wherein a plurality of the regions being formed by dividing a reactor core, an abnormal output removing section 4 for removing the output from the conversion section having a failure, when the failure has occurred and outputting an output to this effect and an interpolation calculating section 11 for making an interpolation for the output signal, corresponding to the quantity-of-generated-heat conversion section, having the failure by substituting the output signal of the gamma ray thermometer located at a symmetrical position in an axial and a radial directions of the core for it. COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2009158529A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2009158529A
公开(公告)日：2009-07-16
申请号：JP2007331761
申请日：2007-12-25
申请人： Toshiba Corp , 株式会社東芝
发明人： KITO MASARU , KATSUMATA RYUTA , KITO TAKASHI , FUKUZUMI YOSHIAKI , TANAKA HIROYASU , MATSUOKA YASUYUKI , KOMORI YOSUKE , ISHIZUKI MEGUMI , ITO HITOSHI , AOCHI HIDEAKI , NITAYAMA AKIHIRO
IPC分类号： H01L21/8247 , G11C16/02 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of reducing the fear of read disturb. SOLUTION: Memory strings are formed by connecting in series a plurality of electrically rewritable memory cells, a bit line side selection transistor and a source line side selection transistor. A columnar semiconductor functions as a channel region of the memory strings and is formed so as to extend in a vertical direction to a semiconductor substrate. A conductive layer is formed in parallel to the semiconductor substrate, and functions as a word line of the memory cells, and a selection gate line of the bit side selection transistor and the source line side transistor. A plurality of bit lines are connected to an upper end of the columnar semiconductor. On the semiconductor, source lines are formed so as to sandwich an element isolation insulation film in a first direction as a longitudinal direction and a second direction perpendicular to the first direction. The source lines are connected to a lower end of the semiconductor substrate. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够降低对读取干扰的恐惧的非易失性半导体存储器件。解决方案：通过串联连接多个电可重写存储器单元，位线侧选择晶体管和源极线选择晶体管来形成存储器串。柱状半导体用作存储器串的沟道区，并且形成为在垂直方向上延伸到半导体衬底。导电层与半导体衬底平行地形成，并且用作存储单元的字线，以及位侧选择晶体管和源极线侧晶体管的选择栅极线。多个位线连接到柱状半导体的上端。在半导体上，源极线被形成为将元件隔离绝缘膜沿着与第一方向垂直的纵向和第二方向作为第一方向夹着元件隔离绝缘膜。源极线连接到半导体衬底的下端。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2006210699A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006210699A
公开(公告)日：2006-08-10
申请号：JP2005021570
申请日：2005-01-28
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAZAKI HIROYUKI , ITO HITOSHI
IPC分类号： H01L29/78 , H01L29/786
CPC分类号： H01L29/4238 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent deterioration of characteristics of an MIS transistor.
SOLUTION: The device has an MIS transistor which has a gate electrode 7 formed to cross an element region isolated by an isolation region 3 of a semiconductor substrate 1, a source-drain region 17 formed in the semiconductor substrate at both sides of the gate electrode, and an elevated source-drain 15 formed on the source-drain region. The gate electrode is constituted so that the gate length in a boundary between the isolation region and the element region is longer than the gate length in the central part of the element region.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够防止MIS晶体管的特性劣化的半导体器件。解决方案：该器件具有MIS晶体管，其具有形成为跨越由半导体衬底1的隔离区域3隔离的元件区域的栅极电极7，形成在半导体衬底的两侧的半导体衬底中的源极 - 漏极区域17 栅极电极和形成在源极 - 漏极区域上的升高的源极 - 漏极15。栅电极被构成为使得隔离区域和元件区域之间的边界中的栅极长度大于元件区域的中心部分的栅极长度。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2012064754A Nonvolatile semiconductor storage device manufacturing method and nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件制造方法和非易失性半导体存储器件
公开(公告)号：JP2012064754A
公开(公告)日：2012-03-29
申请号：JP2010207812
申请日：2010-09-16
申请人： Toshiba Corp , 株式会社東芝
发明人： HONDA MASASHI , KINOSHITA HIDEYUKI , ITO HITOSHI
IPC分类号： H01L27/115 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device manufacturing method which can form a sufficient amount of silicide while inhibiting defects in a silicide step.SOLUTION: The nonvolatile semiconductor storage device manufacturing method comprises the steps of: forming a memory cell transistor including a floating gate electrode, a first interelectrode insulator film on the floating gate electrode and a control gate electrode on the first interelectrode insulator film; forming a field effect transistor including a lower gate electrode, a second interelectrode insulator film and an upper gate electrode on the second interelectrode insulator film; forming an interlayer insulator film so as to expose top faces of the control gate electrode and the upper gate electrode; etch-backing the control gate electrode and the upper gate electrode such that the top faces of the control gate electrode and the upper gate electrode become lower than a top face of the interlayer insulator film; forming a first conductive film on the whole area of the control gate electrode, the upper gate electrode and the interlayer insulator film; etch-backing the first interlayer insulator film; and silicidating the control gate electrode, the upper gate electrode and the first conductive film by depositing metal thereon.
摘要翻译：要解决的问题：提供一种能够在抑制硅化物步骤中的缺陷的同时形成足够量的硅化物的非易失性半导体存储器件制造方法。解决方案：非易失性半导体存储器件制造方法包括以下步骤：形成包括浮置栅极电极，浮置栅电极上的第一电极间绝缘膜和第一电极间绝缘膜上的控制栅电极的存储单元晶体管; 在所述第二电极间绝缘膜上形成包括下栅电极，第二电极间绝缘膜和上栅电极的场效应晶体管; 形成层间绝缘膜，以露出控制栅电极和上栅电极的顶面; 蚀刻背衬控制栅电极和上栅电极，使得控制栅电极和上栅电极的顶面变得低于层间绝缘膜的顶面; 在控制栅电极，上栅电极和层间绝缘膜的整个区域上形成第一导电膜; 蚀刻背衬第一层间绝缘膜; 以及通过在其上沉积金属来硅化所述控制栅电极，所述上栅电极和所述第一导电膜。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2012038835A Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2012038835A
公开(公告)日：2012-02-23
申请号：JP2010175970
申请日：2010-08-05
申请人： Toshiba Corp , 株式会社東芝
发明人： HONDA MASASHI , ITO HITOSHI , KINOSHITA HIDEYUKI
IPC分类号： H01L27/115 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11526 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which sufficient amount of silicide can be formed in the peripheral circuit region while suppressing growth rate of silicide in a memory cell region, and to provide a method of manufacturing the same.SOLUTION: The nonvolatile semiconductor memory device comprises a semiconductor substrate, a memory cell transistor formed in a memory cell region, and a field effect transistor formed in the peripheral circuit region. The memory cell transistor has a floating gate electrode formed on the semiconductor substrate through a first gate insulating film, a first interelectrode insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the first interelectrode insulating film. The control gate electrode is formed by a plurality of laminated conductive films. The control gate electrode has a barrier film formed on at least one of interfaces among the plurality of laminated conductive films in order to minimize diffusion of metal atoms. A part of the control gate electrode is silicided.
摘要翻译：解决的问题：提供一种非易失性半导体存储器件，其中可以在抑制存储单元区域中的硅化物的生长速率的同时在外围电路区域中形成足量的硅化物，并提供其制造方法。解决方案：非易失性半导体存储器件包括形成在存储单元区域中的半导体衬底，存储单元晶体管和形成在外围电路区域中的场效应晶体管。存储单元晶体管具有通过第一栅极绝缘膜，布置在浮置栅电极上的第一电极间绝缘膜和布置在第一电极间绝缘膜上的控制栅电极而形成在半导体衬底上的浮栅。控制栅电极由多层叠导电膜形成。控制栅电极具有形成在多个层叠导电膜中的至少一个界面上的阻挡膜，以使金属原子的扩散最小化。控制栅电极的一部分被硅化。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2010098235A Non-volatile semiconductor storage device and method of manufacturing the same 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：JP2010098235A
公开(公告)日：2010-04-30
申请号：JP2008269804
申请日：2008-10-20
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUZUMI YOSHIAKI , AOCHI HIDEAKI , KATSUMATA RYUTA , KITO TAKASHI , KITO MASARU , TANAKA HIROYASU , MATSUOKA YASUYUKI , KOMORI YOSUKE , ISHIZUKI MEGUMI , NITAYAMA AKIHIRO , ITO HITOSHI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device whose occupied area is reduced and a method of manufacturing the same. SOLUTION: The non-volatile semiconductor storage device 100 is provided with: memory strings MS; and a projected layer 50 having first width in the row direction and formed at an upper part of a substrate Ba by projection. The memory strings MS are provided with: first to fourth word line conductor layers 31a-31d laminated on the substrate Ba; a memory columnar semiconductor layer 36 formed so as to penetrate the first to fourth word line conductor layers; and an electric charge accumulation layer 35b formed between the first to fourth word line conductor layers 31a-31d and the memory columnar semiconductor layer 36. The first to fourth word line conductor layers 31a-31d are provided with: first to fourth bottoms 311a-311d extending in parallel with the substrate Ba; and first to fourth sides 312a-312d extending upward to the substrate Ba along the projected layer 50 at the ends of the first to fourth bottoms. The width of the projected layer 50 in the row direction is equal to or less than that of a projected layer 50 in the laminated direction. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种占用面积减少的非易失性半导体存储装置及其制造方法。解决方案：非易失性半导体存储装置100具有：存储器串MS; 以及在行方向上具有第一宽度并且通过突出形成在基板Ba的上部的投影层50。存储器串MS设置有：层叠在基板Ba上的第一至第四字线导体层31a〜31d; 形成为贯穿第一至第四字线导体层的记忆柱状半导体层36; 以及形成在第一至第四字线导体层31a-31d和存储柱状半导体层36之间的电荷累积层35b。第一至第四字线导体层31a-31d设置有：第一至第四底部311a-311d 与基板Ba平行延伸; 以及在第一至第四底部的端部处沿着突出层50向上延伸到基板Ba的第一至第四侧312a-312d。投影层50的行方向的宽度等于或小于层叠方向上的投影层50的宽度。版权所有（C）2010，JPO＆INPIT

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