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1. 发明专利

JP2011233042A Calibration control apparatus and calibration control method 审中-公开
标题翻译：校准控制装置和校准控制方法
公开(公告)号：JP2011233042A
公开(公告)日：2011-11-17
申请号：JP2010104395
申请日：2010-04-28
申请人： Toshiba Corp , 株式会社東芝
发明人： CHIBA TAKAO , TAKAHASHI KYOSUKE
IPC分类号： G06F1/06
摘要： PROBLEM TO BE SOLVED: To provide a calibration control apparatus and a calibration control method that can reduce processing time for applicability to practical use by carrying out a simple calibration using the result of a previous calibration process in response to a request for a re-calibration process after a calibration process.SOLUTION: For response data to a calibration request command issued by a request for re-calibration, a plurality of sampling clocks with different phases are selected from a continuous phase range in which valid sampling of sampling clocks detected in the last calibration process is possible and the result of sampling of the selected sampling clocks is verified to carry out a simple calibration.
摘要翻译：要解决的问题：提供一种校准控制装置和校准控制方法，该校准控制装置和校准控制方法可以通过根据先前的校准过程的结果执行简单校准来减少适用于实际使用的处理时间，校准过程后重新校准过程。
解决方案：对于通过重新校准请求发出的校准请求命令的响应数据，从连续相位范围中选择具有不同相位的多个采样时钟，其中在最后校准过程中检测到的采样时钟的有效采样是可能的，并且验证所选择的采样时钟的采样结果，以执行简单的校准。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2011233043A Calibration processing control device and calibration processing control method 审中-公开
标题翻译：校准处理控制装置和校准处理控制方法
公开(公告)号：JP2011233043A
公开(公告)日：2011-11-17
申请号：JP2010104396
申请日：2010-04-28
申请人： Toshiba Corp , 株式会社東芝
发明人： CHIBA TAKAO , TAKAHASHI KYOSUKE
IPC分类号： G06F13/12
摘要： PROBLEM TO BE SOLVED: To provide a calibration processing control device and a calibration processing control method for achieving calibration processing which is suitable for a practical use by setting the phase range of a clock available for the sampling of reception data adaptively to the situation or transmission conditions of a processing line or the like.SOLUTION: A first state that the phase setting of a sampling block is determined based on the validity of the result of the successive variation and sampling of the phase of the sampling clock as for calibration data corresponding to a calibration command and a second state that the phase setting of the sampling clock is determined based on the validity of the result of the successive variation and sampling of the phase of the sampling clock as for a command response and calibration data corresponding to the calibration command, are selectively switched according to external conditions.
摘要翻译：要解决的问题：提供一种校准处理控制装置和校准处理控制方法，用于通过将可用于接收数据的采样的时钟的相位范围自适应地设置为适于实际使用的校准处理来适应处理线等的状况或发送条件。解决方案：基于对应于校准命令的校准数据的采样时钟的相位的连续变化和采样的结果的有效性确定采样块的相位设置的第一状态，第二状态说明采样时钟的相位设置基于连续变化的结果的有效性以及采样时钟的相位采样以及对应于校准命令的校准数据，根据外部条件。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2011113521A Host controller, and image processing apparatus and method 审中-公开
标题翻译：主控制器和图像处理装置和方法
公开(公告)号：JP2011113521A
公开(公告)日：2011-06-09
申请号：JP2009272347
申请日：2009-11-30
申请人： Toshiba Corp , 株式会社東芝
发明人： CHIBA TAKAO , TAKAHASHI KYOSUKE
IPC分类号： G06K17/00 , G06F13/10
摘要： PROBLEM TO BE SOLVED: To reduce the load of processing generated in a device driver side, concerning calibration processing between a memory card and a host controller.
SOLUTION: The host controller includes: a calibration command issuing means for issuing one calibration command for a memory card according to a calibration command issuing request from the device driver; a data receiving means for sampling data for calibration that is returned from the memory card in response to the calibration command under the clock phase setting for sampling of data received from the device driver for controlling the host controller; a received data validity decision means for determining the validity of data for calibration received by the data receiving means; and a notification means for notifying the device driver of decision results by the received data validity decision means.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了减少在设备驱动器侧产生的处理负载，涉及存储卡和主机控制器之间的校准处理。主控制器包括：校准命令发出装置，用于根据来自设备驱动程序的校准命令发出请求发出用于存储卡的一个校准命令; 一个数据接收装置，用于从时钟相位设置中响应于校准命令从存储卡返回的用于校准的数据，用于从用于控制主机控制器的设备驱动器接收的数据的采样; 用于确定由数据接收装置接收的用于校准的数据的有效性的接收数据有效性判定装置; 以及通知装置，用于通过接收到的数据有效性判定装置通知设备驱动器的判定结果。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2001014108A DISK STORAGE DEVICE AND DISK CONTROLLER 失效
公开(公告)号：JP2001014108A
公开(公告)日：2001-01-19
申请号：JP18705499
申请日：1999-06-30
申请人： TOSHIBA CORP
发明人： CHIBA TAKAO , ICHIKAWA YASUHIKO
IPC分类号： G06F3/06 , G11B19/00
摘要： PROBLEM TO BE SOLVED: To provide a device for reducing power consumption as a result by supplying the clock of an absolute minimum frequency in an operation state not requiring a high frequency clock in a disk controller. SOLUTION: In this disk controller used for the disk drive of an HDD or the like, the frequency clock of a clock generation circuit 4 is controlled corresponding to the operation state of a data transfer control circuit accompanying the processing of a command from a host system. The clock generation circuit 4 supplies the clock of a high frequency to a host interface 2 at the time of a data transfer processing. Also, after a command processing is ended, the clock of the absolute minimum frequency is generated and supplied to the host interface 2.

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