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1. 发明专利

JPH0287306A MAGNETIC DISK DEVICE 失效
公开(公告)号：JPH0287306A
公开(公告)日：1990-03-28
申请号：JP23820188
申请日：1988-09-22
申请人： TOSHIBA CORP , TOSHIBA COMPUTER ENG
发明人： KAIDA KATSUHIKO , UCHIUMI TORU
IPC分类号： G11B5/09
摘要： PURPOSE:To prevent the decrease in the peak value of the highest frequency by preventing the interference of a low pass filter by a buffer amplifier, using a lead filter so as to increase the highest frequency component of a readout signal and adjusting the relation of the between a gate channel and a time channel by a delay line. CONSTITUTION:An output signal of an input amplifier 1 passes through a low pass filter 2 and inputted to a time channel and a gate channel respectively. The gate channel is provided with a buffer amplifier 10 and a lead filter 11 and an output signal of the input amplifier 1 is inputted to the buffer amplifier 10. The output of the buffer amplifier 10 is inputted to the lead filter 11 and since the lead filter has a bypass characteristic or a band pass characteristic, the maximum frequency component of the output signal from the buffer amplifier 10 is increased. Thus, a waveform shown in figure is obtained from the output signal of the buffer amplifier 10 at the inner circumferential side with a high recording density by using the lead filter 11. Thus, the peak of the highest frequency is averaged.

2. 发明专利

JPS6355772A MAGNETIC RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPS6355772A
公开(公告)日：1988-03-10
申请号：JP19943086
申请日：1986-08-26
申请人： TOSHIBA CORP , TOSHIBA COMPUTER ENG
发明人： OKAMURA HIROSHI , UCHIUMI TORU
IPC分类号： G11B19/12 , G11B19/02
摘要： PURPOSE:To prevent data from being written to an unsuitable memory medium by identifying the data recording density of the memory medium from a voltage in proportion to the frequency of a read signal obtained from a magnetic head. CONSTITUTION:An analog signal that the magnetic head reads out of the memory medium is supplied to an F/V comparator 2 through a preamplifier 1. The comparator 2 outputs a voltage in proportion to the frequency of he given analog signal. The output is in proportion to the data recording density. Consequently a mode identification circuit 3 identifies the write mode of the memory medium, that is, the recording medium, from the output of the comparator 2. A comparator 4 compares the identified write mode with the mode inherent to a device from a controller 5. If the comparison shows that they are different, the comparator 4 outputs at signal to instruct write regulations to the controller 5. Thus data is not written to the unsuitable memory medium.

3. 发明专利

JPH0281367A DATA REPRODUCING DEVICE FOR RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH0281367A
公开(公告)日：1990-03-22
申请号：JP23264688
申请日：1988-09-19
申请人： TOSHIBA CORP , TOSHIBA COMPUTER ENG
发明人： UCHIUMI TORU , ASAI KENJI
IPC分类号： G11B20/10
摘要： PURPOSE:To reproduce the servo signal of a proper level surely and at a high speed by providing a control voltage calculating means for servo and a control voltage setting means for servo. CONSTITUTION:The title device provides a control voltage calculating means for servo to compare the level of a servo signal read from a head 10 with the reference value determined beforehand at the initial setting mode time and store the data of the control voltage of an AGC amplifying circuit set when the compared result is in the allowable range into a memory 32. Further, a control voltage setting means for servo to read the data of the control voltage stored into the memory 32 and set the control voltage to the AGC amplifying circuit when a servo signal is outputted from a head 10 at the time of the ordinary action mode. Thus, the proper level servo signal can be reproduced surely and at a high speed, and as the result, based on the data face servo data, the positioning control of the magnetic head can be executed surely and at a high speed.

4. 发明专利

JPH09223010A MICROPROCESSOR AND ITS PROCESSING METHOD 失效
公开(公告)号：JPH09223010A
公开(公告)日：1997-08-26
申请号：JP2934896
申请日：1996-02-16
申请人： TOSHIBA CORP
发明人： UCHIUMI TORU
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To change the frequency of a clock signal and to improve the total processing speed of a microprocessor by using a clock control circuit which changes the frequency of a clock to be supplied to each pipeline stage based on the time information held by each pipeline holding means. SOLUTION: A clock control circuit 353 changes the frequency of a clock signal 354 based on the time information held in the time information fields 321a, 331a and 341a of stages E, M and W respectively. Only the instruction that is held by an input register of the stage M requires 6 cycles of a source clock 352 for its execution, and the instructions of stages E and W can operate by 4 cycles of the source clock 352 respectively. Under such conditions, the type of instruction that is held by the input register of a stage D cannot be discriminated and the time required for its execution is fixed at 4 cycles of the source clock 352. The circuit 353 does not raise the clock signal 354 before the execution is over for the instruction of the stage M that requires the longest time.

5. 发明专利

JP2002100737A SEMICONDUCTOR IC AND METHOD OF DESIGNING THE SEMICONDUCTOR IC 失效
公开(公告)号：JP2002100737A
公开(公告)日：2002-04-05
申请号：JP2000290524
申请日：2000-09-25
申请人： TOSHIBA CORP
发明人： OISHI NORIKAZU , MORI TOSHIAKI , USAMI MASAYOSHI , UCHIUMI TORU , HATANAKA KOJIRO
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To make a power-saving operation available by suppressing increase in consumed power, caused by an adjustment produced to a line delay time between modules by inserting repeaters. SOLUTION: In a semiconductor IC, a transmission delay on a signal line is adjusted by means of repeaters, to make adjustment for a signal transmission timing between modules. At least one of the repeaters is replaced by a guard logic for passing or blocking a signal. In a period, during which the modules at the downstream side of the guard logic are not conducting a signal processing operation, the guard logic is cut off, to prevent signals from being inputted into the modules downstream from the guard logic, thus stopping drive signals for active elements and suppressing the increase in consumped power.

6. 发明专利

JP2001229678A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2001229678A
公开(公告)日：2001-08-24
申请号：JP2000354677
申请日：2000-11-21
申请人： TOSHIBA CORP
发明人： UCHIUMI TORU
IPC分类号： G06F12/08 , G06F12/02 , G11C8/00 , G11C8/04 , G11C11/41 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory in which access sped can be increased. SOLUTION: Immediate values in which values are decided in each different timings and a base address are inputted to an adder and a word line is selected, and access speed is reduced by being restricted by the base address whose value is decided slowly. On the contrary, only an immediate value of which decision of a value is fast is inputted to an address decoder AD and decoding is performed, after that, rotation is performed by using the base address whose value is decided with delayed timing and a word line WL is selected. Thereby, decoding processing can be started without waiting for the time when a value of a base address is decided, and the whole access speed is increased.

7. 发明专利

JPS63141131A PIPELINE CONTROL SYSTEM 失效
公开(公告)号：JPS63141131A
公开(公告)日：1988-06-13
申请号：JP28759886
申请日：1986-12-04
申请人： TOSHIBA CORP
发明人： UCHIUMI TORU
IPC分类号： G06F9/38
摘要： PURPOSE:To increase the processing speed of an instruction, by jumping a stage to which no input is required corresponding to the content of the instruction by the instruction to be executed and processed without changing the processing order of the instruction in a pipeline instruction processing. CONSTITUTION:In a jumping operation where an internal instruction requires no calculation of execute address, when a preceding internal instruction is stored and held in a second instruction register 9, and if the preceding instruction is transferred to the next stage with the next clock signal which executes a decoding operation at an instruction decoder 1, the output of a second flip-flop 15 represents that the second instruction register 9 is set at a vacant state, and the output of the second flip-flop 15 is supplied to a control circuit 17. In such a way, a control signal is supplied to a selector 11, and the internal instruction outputted from the instruction decoder 1 jumps a first instruction register 3, and is stored and held in the second instruction register 9 via the selector 11.

8. 发明专利

JPS6386032A EFFECTIVE ADDRESS CALCULATING DEVICE 失效
公开(公告)号：JPS6386032A
公开(公告)日：1988-04-16
申请号：JP23232086
申请日：1986-09-30
申请人： TOSHIBA CORP
发明人： UCHIUMI TORU
IPC分类号： G06F12/02 , G06F9/355
摘要： PURPOSE:To omit an effective address calculated at an executing stage by using an executing address arithmetic unit which can qualify the result of addition qualified by an address qualifying element with another address qualifying element. CONSTITUTION:The displacement shown from a reference address is stored in a register 10 with an instruction for calculation of an executing address together with the reference address stored in a base register 12. Then the reference address is latched by registers 42 and 44 via a selector 62. The registers 10, 42 and 44 are put together by a 3-input adder 50 for calculation of the executing address. The result of this addition is delivered to an executing address register 20 as well as to a selector 60. A state shift control circuit 34 controls both selectors 60 and 62 based on the mode value of a mode register 18 and at the same time controls calculation of the executing address with reference to flip-flops 30 and 32.

9. 发明专利

JPH04227327A LOW POWER CONSUMPTION TYPE PROGRMMABLE LOGIC ARRAY AND INFORMATION PROCESSING UNIT USING IT 失效
公开(公告)号：JPH04227327A
公开(公告)日：1992-08-17
申请号：JP9757991
申请日：1991-04-26
申请人： TOSHIBA CORP
发明人： HORIE ATSUSHI , UCHIUMI TORU
IPC分类号： G06F1/32 , G06F1/26 , G06F9/30 , H03K19/00 , H03K19/177
摘要： PURPOSE:To reduce the power consumption of a programmable logic array(PLA) by interrupting supply of power from a power supply under the control of an enable signal when a product term line and an output line of the PLA are inactive. CONSTITUTION:When a PLA is not in use, an enable signal of a low level is given to an enable terminal EN. Thus, one input terminal of each AND gate represented by an AND gate G10 goes to a low level and a level of all input lines goes to a low level independently of the level of the input signal given to input terminals IN1-INn. Thus, all array TRs whose gate terminal connects to input lines such as an array TR T10 are nonconductive.

10. 发明专利

JPH0217544A INFORMATION PROCESSOR 失效
公开(公告)号：JPH0217544A
公开(公告)日：1990-01-22
申请号：JP16685588
申请日：1988-07-06
申请人： TOSHIBA CORP
发明人： UCHIUMI TORU
IPC分类号： G06F9/38 , G06F11/00 , G06F11/14 , G06F11/20 , G06F12/16
摘要： PURPOSE:To save plural error addresses at the time of the occurrence of a bus error cycle by storing the address of error, which occurs at the time of reading an external storage, in a private storage means to perform interrupt handling. CONSTITUTION:The write address on an internal bus 11 is stored in a register 1 designated by a select signal in accordance with execution of a micro instruction. Write data is stored in a register 7 similarly to start a write cycle. When a bus cycle error occurs to give an error signal to a control logic 23, a signal EAR is given to an error address storage register EAR 9 from the control logic 23. Then, the error address is copied in the EAR 9, and an interrupt signal is outputted to a micro instruction control part simultaneously. After the interrupt signal is outputted, the error address stored in the EAR 9 is pushed to a stack through the internal bus 11.

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