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1. 发明专利

JPH05175285A HYBRID SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05175285A
公开(公告)日：1993-07-13
申请号：JP34280891
申请日：1991-12-25
申请人： TOSHIBA CORP , HITACHI CABLE
发明人： OTSUKA MASASHI , NAGANO JUNYA , TAKAGI MASAHARU , YAMAGUCHI KENJI
IPC分类号： H01L21/603 , H01L21/60 , H05K1/09 , H05K3/32
摘要： PURPOSE:To provide a hybrid semiconductor device which can be easily assembled and, at the same time, which can be manufactured at a low cost. CONSTITUTION:A metallic layer pattern 15 at a lead joining section on a substrate 14 is composed of a copper pattern 21, nickel layer 22 plated on the pattern 21, and gold layer 23 plated on the layer 22 and a tin layer 24 is plated on the front end section of an inner lead 12. The inner lead 12 is electrically connected to the pattern 15 through a gold-tin eutectic layer 25 by thermocompression bonding the lead 12 to the pattern 15.

2. 发明专利

JP2011066181A Printed wiring board and method of manufacturing the same 有权
标题翻译：印刷线路板及其制造方法
公开(公告)号：JP2011066181A
公开(公告)日：2011-03-31
申请号：JP2009215263
申请日：2009-09-17
申请人： Hitachi Cable Fine Tech Ltd , Hitachi Cable Ltd , 日立電線ファインテック株式会社 , 日立電線株式会社
发明人： IMAI NOBORU , SAEKI MASAHIKO , MORITA MASAMIKI , OTOMO KATSUYA , YAMAGUCHI KENJI
IPC分类号： H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board allowing for stable and accurate appearance quality check of the opening pattern of a via or stable and accurate check for the presence or absence of the occurrence of elution of copper (Cu) at a land exposed at an opening of a via which has strong correlation with the occurrence of defects in an opening pattern of such a via, and to provide a method of manufacturing the printed wiring board. SOLUTION: In the printed wiring board, at least one of copper wiring patterns 3 is connected to the land 5 exposed at the opening of the via 7 and to a lead section 9 for detecting elution of copper (Cu), provided in such a manner that the surface is exposed with an area smaller than the exposed area of the land 5 at a position differing from that of the land 5. An electroless tin (Sn) plated film is formed on the surface of the lead section 9 for detecting elution of copper (Cu). COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供印刷线路板，其允许对通孔的开口图案的稳定和准确的外观质量检查，或者稳定和准确地检查是否存在铜（Cu）在在与通孔的开口图案中的缺陷的发生强烈相关的通孔的开口处露出的露台，并且提供制造印刷电路板的方法。解决方案：在印刷电路板中，铜布线图案3中的至少一个连接到在通孔7的开口处露出的焊盘5和用于检测铜（Cu）的洗脱的引线部分9，这样一种方式使得表面在与焊盘5的位置不同的位置处以小于焊盘5的暴露面积的面积曝光。在引线部分9的表面上形成无电镀锡（Sn），用于检测铜（Cu）的洗脱。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2010027801A Cof tape, and method of manufacturing the same 审中-公开
标题翻译： COF胶带及其制造方法
公开(公告)号：JP2010027801A
公开(公告)日：2010-02-04
申请号：JP2008186342
申请日：2008-07-17
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： YAMAGUCHI KENJI , KASHIWABARA FUMITAKA
IPC分类号： H01L21/60
CPC分类号： H01L24/81 , H01L2224/81193 , H01L2224/81805 , H01L2924/01322 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a COF tape which does not thicken cross-sections of wiring and an Au bump made when bonded to a semiconductor chip by Au-Sn eutectic bonding, and accordingly, does not narrow a space between wirings. SOLUTION: The COF tape has a wiring pattern 2 made of copper by a subtractive method on one surface of an insulating tape base 1, and the wiring 3 formed by etching is sectioned in a suitable trapezoid shape to secure necessary size precision of a top width T of the wiring. The number of etching factors Ef of the wiring pattern 2 in the subtractive method is 2 to 4, the top width T of the wiring 3 of the wiring pattern 2 is 2 to 6 μm, and a wiring pitch is ≤30 μm. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种COF带，其不会在通过Au-Sn共晶接合与半导体芯片接合时产生的布线横截面和Au凸块变厚，因此不会缩小布线之间的空间。解决方案：COF带在绝缘带基体1的一个表面上具有通过减色法由铜制成的布线图案2，并且通过蚀刻形成的布线3被切成适当的梯形形状，以确保必要的尺寸精度布线的顶部宽度T。减法法中的布线图案2的蚀刻因子Ef的数量为2〜4，布线图案2的布线3的顶部宽度T为2〜6μm，布线间距为≤30μm。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2005294539A Tape carrier for semiconductor device and its manufacturing method 审中-公开
标题翻译：用于半导体器件的带状载体及其制造方法
公开(公告)号：JP2005294539A
公开(公告)日：2005-10-20
申请号：JP2004107640
申请日：2004-03-31
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： YAMAGUCHI KENJI , SUZUKI KATSUMI
IPC分类号： H05K3/16 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a tape carrier for semiconductor device in which a defect of wiring is suppressed even if a pitch of copper wiring is narrowed, and to provide the manufacturing method of the carrier.
SOLUTION: An adhesive layer 3 with thickness of 2 to 8μm is applied to one face of a polyimide film 1. A seed layer 4 by sputtering is formed on the adhesive layer 3 with an Ni-Cr alloy layer and a copper layer. A copper plating layer 6 is formed by electroplating on the seed layer 4. A copper wiring pattern is formed whose wiring pitch is 5 to 30 μm. A semiconductor element is loaded on the copper wiring pattern by flip chip bonding.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供即使铜布线的间距变窄也能够抑制布线的缺陷的半导体装置的带载体，并且提供载体的制造方法。解决方案：将厚度为2至8μm的粘合剂层3施加到聚酰亚胺膜1的一个面上。通过溅射形成种子层4，在Ni-Cr合金层和铜层上形成粘合剂层3 。通过在种子层4上电镀形成镀铜层6.形成布线间距为5〜30μm的铜布线图案。半导体元件通过倒装芯片接合装载在铜布线图案上。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005285884A Carrier tape for semiconductor device manufacturing method, and etching processing device therefor 有权
标题翻译：用于半导体器件制造方法的载体带及其蚀刻处理装置
公开(公告)号：JP2005285884A
公开(公告)日：2005-10-13
申请号：JP2004094048
申请日：2004-03-29
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： YAMAGUCHI KENJI
IPC分类号： H05K3/06 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To enable inhibiting of the width of a copper wiring from becoming thinner, and to obtain superior linearity in etch processing, to produce a copper wiring pattern of a TAB tape with a target fine pitch of 5μm to 30μm.
SOLUTION: The carrier tape for semiconductor device manufacturing method comprises the steps of applying a photoresist on the copper layer, using a two-layer tape or a three-layer tape; forming a wiring pattern, after performing exposing, developing, etching, and photoresist peeling processes: and applying an Sn-plating treatment for flip-chip bonding the semiconductor device to the wiring pattern. In the etching process, the photoresist pattern face of the two-layer tape or three-layer tape is passed in an etching solution 4 that is filled in an etching bath 7 and flows in a direction opposite to the tape-carrying direction, in order to form the wiring pattern of a 5 to 30 μm fine pitch.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题为了能够抑制铜布线的宽度变薄，并且为了获得优异的蚀刻处理线性，制造目标细间距为5μm至30μm的TAB带的铜布线图案。解决方案：用于半导体器件制造方法的载带包括以下步骤：使用双层带或三层带在铜层上施加光致抗蚀剂; 在进行曝光，显影，蚀刻和光刻胶剥离处理之后，形成布线图案;以及施加用于将半导体器件倒装芯片接合到布线图案的Sn镀层处理。在蚀刻工艺中，双层带或三层带的光致抗蚀剂图案面通过蚀刻溶液4，其被填充在蚀刻槽7中，并沿与带传送方向相反的方向依次流动以形成5至30μm细间距的布线图案。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2004304046A Film carrier tape for cof 有权
公开(公告)号：JP2004304046A
公开(公告)日：2004-10-28
申请号：JP2003097024
申请日：2003-03-31
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： SUZUKI KATSUMI , YAMAGUCHI KENJI
IPC分类号： H01L21/60
CPC分类号： H01L2224/50
摘要： PROBLEM TO BE SOLVED: To solve such a problem that a COF tape is adhered to a heating tool, resulting in a joint failure of a lead and a bump because the heating tool is heated at a high temperature in conventional COF bonding. SOLUTION: The film carrier tape for COF used for COF bonding is formed by forming an optional wiring pattern on a tape-like insulation film and heating/press-fitting a lead with the wiring pattern to a bump formed on a semiconductor chip with the insulation film in between at a specified temperature by using a heating tool. A backing film having a dynamic elastic modulus of 10.0 GPa or more at 300-400°C of the heating tool is joined with a rear surface of the insulation film. COPYRIGHT: (C)2005,JPO&NCIPI

7. 发明专利

JP2004207550A Tape carrier for semiconductor device 审中-公开
公开(公告)号：JP2004207550A
公开(公告)日：2004-07-22
申请号：JP2002375830
申请日：2002-12-26
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： SUZUKI KATSUMI , YAMAGUCHI KENJI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide a tape carrier for a semiconductor device by which defective COF bonding is removed and the temperature of a heating tool is increased, and in which an insulating film bonded in a short time is used as a COF tape base material. SOLUTION: In the tape carrier for the semiconductor device, a wiring pattern 10 containing a lead for COF connection is formed on the tape base material 1 composed of the insulating film made of a resin and the lead 10b for the wiring pattern is plated 11 for being heat-joined to a semiconductor chip 7 by pressing by the heating tool 9 from a surface on the reverse side of the tape base material in the lead 10b, a material having a dynamic elastic modulus of 1.5 GPa or more is used as the insulating film constituting the tape base material 1. COPYRIGHT: (C)2004,JPO&NCIPI

8. 发明专利

JP2002118154A TAB TAPE AND SEMICONDUCTOR DEVICE USING THE SAME 失效
公开(公告)号：JP2002118154A
公开(公告)日：2002-04-19
申请号：JP2000308084
申请日：2000-10-06
申请人： HITACHI CABLE
发明人： YAMAGUCHI KENJI , KOIZUMI TOYOHARU
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a TAB tape for which existing manufacturing equipment can be used without modification or alteration, and with which yield and productivity are not degraded while excellent stability in size results in manufacturing, and a semiconductor device using the same. SOLUTION: This TAB tape 11 is constituted by an insulating film 1 having an L value of 35 or larger indicating transparency, a copper foil layer 5 that forms copper wiring patterns 5A adhered to the insulating film 1, adhesives 2, 4 having a prescribed range of water absorption coefficient and of glass transition temperature, and a low-expansibility aramid tape 3 having the L value of 35 or larger and adhered to the insulating film 1 with the adhesive 4.

9. 发明专利

JP2001274203A BIMETAL SUBSTRATE AND BGA STRUCTURE 失效
公开(公告)号：JP2001274203A
公开(公告)日：2001-10-05
申请号：JP2000088512
申请日：2000-03-24
申请人： HITACHI CABLE
发明人： YAMAGUCHI KENJI , KOIZUMI TOYOHARU
IPC分类号： H05K1/11 , H01L21/60 , H01L23/12 , H05K1/03 , H05K3/00 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a bimetal substrate and BGA structure that reduce manufacturing processes by carrying out hole-plugging on a blind via hole, and to improve productivity and reliability. SOLUTION: In the bimetal substrate, where a blind via hole 17 is formed by a laser beam 7 on a copper foil surface, at one surface of the configuration of copper foil 1/a base material 2/copper foil 4 for composing a double-sided copper covering laminated sheet with no adhesive layers, and Cu plating 13 is applied in the blind via hole 17 for electric conduction, and only the opening part of the blind via hole 17 is subjected to Cu plating 13. After that, Ni plating 18 and Au plating 8 are applied successively for plugging the blind via hole 17.

10. 发明专利

JP2001189400A BGA-TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001189400A
公开(公告)日：2001-07-10
申请号：JP37139799
申请日：1999-12-27
申请人： HITACHI CABLE
发明人： YAMAGUCHI KENJI , SAEKI MASAHIKO
IPC分类号： H01L23/12 , H01L21/52 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a BGA-type semiconductor device, in which stripping of a layer is prevented at the time of reflow. SOLUTION: An adhesive 4, having water absorption of 0.8-2.7%, is used for bonding the insulation tape 2 of a TAB tape 1 and a wiring layer 3. The insulation tape 2 has water absorption rate of 1.5-2.7% and steam permeability of 2 g/m2.24 hr or higher.

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