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1. 发明专利

JP2007232977A Decoder circuit and liquid crystal driving device using the decoder circuit 审中-公开
标题翻译：使用解码器电路的解码器电路和液晶驱动器件
公开(公告)号：JP2007232977A
公开(公告)日：2007-09-13
申请号：JP2006053607
申请日：2006-02-28
申请人： Toshiba Corp , 株式会社東芝
发明人： TAGUCHI TAKASHI
IPC分类号： G09G3/36 , G02F1/133 , G09G3/20
CPC分类号： G09G3/3688 , G09G2310/0289
摘要： PROBLEM TO BE SOLVED: To provide a decoder circuit which has a signal level conversion function and can be constituted of the small number of transistors, and to provide a liquid crystal driving device using the decoder circuit.
SOLUTION: The decoder circuit 1 divides 6-bit input signals D0 to D5 being in a low voltage level into three bit groups and controls switching of a MOS transistor switch group 3A which has a hierarchical structure of three hierarchies and is operated with a high voltage, by three level shift type decoders 21A to 23A which decode two-bit input signals of respective bit groups to output results in a high voltage level, whereby the decoder circuit 1 selects and outputs one from 2
6 analog inputs. A liquid crystal driving device 1000 supplies a reference voltage selected from 2
6 reference voltages V1 to V64 for gradation display, which a reference voltage generation circuit 100 generates, by the decoder circuit 1 to a liquid crystal device as a gradation display voltage.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有信号电平转换功能并且可以由少量晶体管构成的解码器电路，并提供使用解码器电路的液晶驱动装置。解决方案：解码器电路1将处于低电压电平的6位输入信号D0至D5分为三位组，并且控制具有三层次结构的MOS晶体管开关组3A的切换并且与由三位移位类型解码器21A至23A构成的高电压，其解码各位组的两位输入信号，以将结果输出为高电压电平，由此解码器电路1从2 < SP>模拟输入。液晶驱动装置1000将由解码电路1产生的参考电压产生电路100的两个参考电压V1至V64的参考电压V1至V64提供给液晶装置，作为灰度显示电压。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2005017933A Reference voltage selecting circuit and plane display device 有权
标题翻译：参考电压选择电路和平面显示器件
公开(公告)号：JP2005017933A
公开(公告)日：2005-01-20
申请号：JP2003185484
申请日：2003-06-27
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： TAGUCHI TAKASHI , CHIBA MITSUHIRO
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , H03M1/68
摘要： PROBLEM TO BE SOLVED: To decrease a circuit scale without decreasing the number of gradations.
SOLUTION: A D/A converting circuit has gate lines 8 and diffusion layers 9 which are arranged in a lattice shape and when an arbitrary MOS transistor Q1 arranged at an intersection of a gate line 8 and a diffusion layer 9 turns on, diffusion layers 9 on the right and left sides of the position of the above MOS transistor Q1 conduct through the MOS transistor Q1. When the D/A converting circuit 5 is laid out, four kinds of voltage candidate selection parts 11a to 11d selected with low-order two bits of a digital signal are arranged in a Y direction and a final voltage selection part 12 selected with high-order two bits of the digital signal is arranged in an X direction, thereby the number of diffusion layers 9 can greatly be decreased to decrease the number of MOS transistors Q1 arranged at the intersections of the diffusion layers 9 and gate lines 8, and the number of the diffusion layers can greatly be decreased to make the formation area of the D/A converting circuit 5 small.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：减小电路规模而不减少灰度数。解决方案：AD / A转换电路具有栅极线8和布置成格子状的扩散层9，并且当布置在栅极线8和扩散层9的交叉点处的任意MOS晶体管Q1导通时，扩散上述MOS晶体管Q1的位置的左右两侧的层9通过MOS晶体管Q1导通。当布置D / A转换电路5时，在Y方向上布置四个选择数字信号的低位2位的电压候选选择部分11a至11d，并且选择高电平的最终电压选择部分12，数字信号的2位的顺序被布置在X方向上，从而可以大大减少扩散层9的数量，以减少布置在扩散层9和栅极线8的交点处的MOS晶体管Q1的数量，并且数量可以大大降低扩散层，使D / A转换电路5的形成面积小。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JPH1130974A SEMICONDUCTOR FOR DRIVING CONTROL FOR LIQUID CRYSTAL DISPLAY DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JPH1130974A
公开(公告)日：1999-02-02
申请号：JP18669897
申请日：1997-07-11
申请人： TOSHIBA CORP
发明人： TAGUCHI TAKASHI , ITAKURA TETSURO
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To provide a liquid crystal display device of which power consumption is made as much as small and also signal delays are not generated at the time of invertingly driving a liquid crystal panel. SOLUTION: This liquid crystal display device is provided with a digital controller 1, a level converting circuit 2, D/A converters 3, 4, a liquid crystal panel 5 and capacitors C and in the D/A converter 3, charging control circuits 31 are provided corresponding to respective capacitors C. The charging control circuits 31 have switches SW1 and diodes D which are connected in parallel and inverters INV. Ons and offs of the switches SW1 are controlled in accordance with a changeover signal from the digital controller 1. The switches SW1 are changed to on in the blacking period after the display of one horizontal line and when the switches SW1 are turned on, capacitors C are charged. Levels of digital pixel data outputted from the digital controller 1 are converted in accordance with voltages between electrodes of capacitors C by a law of charge preservation.

4. 发明专利

JPH0772943A CONSTANT VOLTAGE CIRCUIT 失效
公开(公告)号：JPH0772943A
公开(公告)日：1995-03-17
申请号：JP22023593
申请日：1993-09-03
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： KURODA TADASHI , KAJIWARA EIJI , TAGUCHI TAKASHI , YOSHIDA HIROSHI , UCHIDA HIDEAKI
IPC分类号： G05F1/56 , G05F3/24 , G11C11/407 , H03G3/10
摘要： PURPOSE:To provide a constant voltage circuit capable of obtaining constant voltage by suppressing the influence of the fluctuation of power supply voltage without causing the enlargement of a circuit scale. CONSTITUTION:This circuit is provided with a bias circuit 1 generating bias voltage Bias 1 and Bias 2 by receiving power supply voltage, a reference voltage generation circuit 2 generating reference voltage Vref by receiving power source voltage and bias voltage 2, and a voltage follower circuit which is provided with a differential amplifying stage 3 and output stages P6, R3, R4 and C1 to output the n-fold voltage of reference voltage Vref by receiving the bias voltage Bias 1 and reference voltage Vref and where reference voltage is inputted to one of the input terminal of the stage 3 and the 1/n voltage of voltage outputted from the voltage follower circuit is inputted to the other input terminal. Thus, voltage outputted from the voltage follower circuit is given to the reference voltage circuit 2 as the power supply voltage.

5. 发明专利

JPH06111600A EPROM 失效
公开(公告)号：JPH06111600A
公开(公告)日：1994-04-22
申请号：JP25482792
申请日：1992-09-24
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： SUWABE HIROYUKI , TAGUCHI TAKASHI , KOBAYASHI TOSHIAKI
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/14
摘要： PURPOSE:To shorten test time by controlling operation of bit lines selecting circuit at 'stop' or 'normal', connecting or separating bit lines to/from first elements, and discriminating whether memory cells are normal or not considering potential of each other end of first element, when it is in a blank check mode or modes besides this mode. CONSTITUTION:Bit line selecting elements C0-C03 are normally operated, while bit lines CA0-CA3 are separated from other ends of first elements RU0-RU3 with second elements M0-M3 corresponding to bit lines CA0-CA3, in modes besides a blank check mode. Operation of elements C0-C3 is stopped, bit lines CA0-CA3 are separated from a writing/reading circuit, and other ends of elements RU0-RU3 are connected to corresponding bit lines in the blank check mode. When a row address signal is inputted in this state, erasing data of memory cells of corresponding rows are read out at the corresponding bit line, and a discriminating circuit NOR1 discriminates whether memory cells are normal or not considering potential of each other end of elements RU0-RU3. Thereby test time is shortened.

6. 发明专利

JP2004184795A Method for designing digital to analog conversion circuit 审中-公开
公开(公告)号：JP2004184795A
公开(公告)日：2004-07-02
申请号：JP2002353332
申请日：2002-12-05
申请人： Toshiba Corp , 株式会社東芝
发明人： SASAKI TAKASHI , TAGUCHI TAKASHI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , H03M1/76
摘要： PROBLEM TO BE SOLVED: To provide a method for designing a digital to analog conversion circuit for achieving a rich gradation.
SOLUTION: The method comprises steps of calculating a transmittancy T by using an offset corresponding to the minimum luminance Lmin or the maximum luminance Lmax; calculating a sample voltage V, based on the transmittancy T; and calculating a resistance value from the sample voltage V. The method divides a curved line indicating a V-T performance into a plurality of ranges, and resistance values for each of the ranges are acquired, respectively, by using this method.
COPYRIGHT: (C)2004,JPO&NCIPI

7. 发明专利

JPH118520A AMPLIFYING CIRCUIT 失效
公开(公告)号：JPH118520A
公开(公告)日：1999-01-12
申请号：JP16125997
申请日：1997-06-18
申请人： TOSHIBA CORP
发明人： ITAKURA TETSURO , TANIMOTO HIROSHI , TAGUCHI TAKASHI
IPC分类号： H03F3/30
摘要： PROBLEM TO BE SOLVED: To maintain stability, even if large voltage variation occurs at the terminal on the opposite side from an amplifying circuit output terminal by obtaining the difference between a voltage generated, corresponding to the output voltage of a voltage amplifying means and the output voltage of the voltage amplifying means and supplying the difference to the gate or base of the transistor of an output means. SOLUTION: A current-generating circuit 4 generates an output voltage, based upon the potential at a 2nd reference potential point Vss by a voltage- generating circuit 5 corresponding to the output voltage of the voltage- amplifying means 1. A subtracting circuit 6 generates the output voltage, based upon the potential at a 2nd power source potential point Vss corresponding to the difference between the output voltage of this voltage-generating circuit 5 and the output voltage of the voltage-amplifying means 1. The output voltage of this subtracting circuit 6 is converted by a current-voltage conversion circuit 3 into voltage, based upon the potential at a 1st power source potential point Vdd and this voltage is applied to the gate of a transistor T21. Consequently, a large output current can be supplied with respect to a load capacitor CL.

8. 发明专利

JPH06164335A BOOSTER CIRCUIT 失效
公开(公告)号：JPH06164335A
公开(公告)日：1994-06-10
申请号：JP30915892
申请日：1992-11-19
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： TAGUCHI TAKASHI , SUWABE HIROYUKI , KOBAYASHI TOSHIAKI
IPC分类号： H03K5/02 , G11C11/407
摘要： PURPOSE:To improve boost efficiency and further to reduce a circuit area by performing a boost operation twice during one cycle of clock signals. CONSTITUTION:The clock signals A is added to one end of a capacitative element 22 connected to a node G and signals for which the signals A are inverted at an inverter 14 are added to the one end of the capacitative element 15 connected to the node D. When the signals phiA are high potential, a source is connected to a power supply VDD, an MOSTr 16 for which the clock signals phi*B are inputted to a gate is conducted and the capacitative element 15 is charged. When, the signals phiA are low potential, the source is connected to the power supply VDD, the MOSTr 23 for which the clock signals phi*C are inputted to the gate is conducted and the capacitative element 22 is charged. When a potential difference is generated at the both ends of the charged capacitative elements 15 and 22 and the potential higher than the potential of the signals phiA is made, the potential higher than the signals phiA appears at the other end of the capacitative elements. Thus, two capacitative elements 15 and 22 are alternately charged during one cycle of the clock signals phiA in this circuit, the boosting efficiency is improved and even the circuit area can be reduced.

9. 发明专利

JPH11126049A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE FOR DRIVING LIQUID CRYSTAL, AND LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JPH11126049A
公开(公告)日：1999-05-11
申请号：JP28873597
申请日：1997-10-21
申请人： TOSHIBA CORP
发明人： TAGUCHI TAKASHI
IPC分类号： G02F1/133 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To secure sufficiently a blanking time even when the length of a wiring used for applying simultaneously a control signal to many elements is made long, by applying a control signal to one end part of a wiring by a blanking circuit and feeding back it from the other end part of a wiring as a trigger. SOLUTION: In a blanking circuit 9, when a load signal LOAD is made to rise, a reset signal R21 outputted from a NOR circuit 91 is applied to one end part of a first wiring. A reset signal R21 ' delayed by a delay time of a wiring is applied to the other input end of an AND circuit 92 through a NOT circuit 93. Therefore, a reset releasing signal R22 outputted from the AND circuit 92 is delayed to rise. When the load signal LOAD falls, a reset releasing signal R22 outputted from the AND circuit 92 is applied to one end part of a second wiring. A reset releasing signal R22 ' delayed by a delay time of a wiring is applied to the other input end of the NOR circuit 91.

10. 发明专利

JP2001133754A LIQUID CRYSTAL DRIVER DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JP2001133754A
公开(公告)日：2001-05-18
申请号：JP31871499
申请日：1999-11-09
申请人： TOPPAN PRINTING CO LTD , TOSHIBA CORP
发明人： CHIBA MITSUHIRO , TAGUCHI TAKASHI
IPC分类号： G09G3/36 , G02F1/133 , G09G3/20
摘要： PROBLEM TO BE SOLVED: To reduce the vertical size by decreasing the number of gradation voltage signal lines and transistors to be numerously arranged in the vertical direction in proportion to the number of gradations in a decoder part. SOLUTION: The liquid crystal driver device and the liquid crystal display device are constituted so as to reduce the vertical size of an area occupied by gradations voltage signal lines by sharing redundant MOS transistors and wiring between adjoining gradation voltage signal lines, in decoding areas of higher order bits A, B except a lower order bit C in a decoder part 20 corresponding to a truth table.

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