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1. 发明专利

JP2000231549A MICROPROCESSOR 失效
公开(公告)号：JP2000231549A
公开(公告)日：2000-08-22
申请号：JP2000029153
申请日：2000-02-07
申请人： TOSHIBA CORP
发明人： SASAHARA SHOJI , KAMURAN MALICK , RAKISSHU AGURAWARU , MICHAEL RAAMU
IPC分类号： G06F12/08 , G06F12/10 , G06F13/28 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a microprocessor which incorporates a RAM available for purposes other than a cache memory and can easily and also fast access the RAM. SOLUTION: This microprocessor is provided with an MMU 3 performing conversion from a virtual address to a physical address and an LSU 4 controlling the execution of a load/store instruction. The LSU 4 has a DCACHE 41 temporarily storing read/write data for an external memory, a SPRAM 42 used for special uses other than a cache and an address generator 43 generating a virtual address for accessing the DCACHE and the SPRAM. The MMU 3 generates a conversion table performing virtual/physical address conversion. Flag information showing whether or not access to the SPRAM is performed is included in the conversion table. When the flag is set, the SPRAM does not have to be allocated to a memory map of a main storage memory because access to the SPRAM is performed unconditionally.

2. 发明专利

JP2002287958A MICROPROCESSOR, AND ITS BRANCH PREDICTING METHOD 失效
公开(公告)号：JP2002287958A
公开(公告)日：2002-10-04
申请号：JP2001093338
申请日：2001-03-28
申请人： TOSHIBA CORP
发明人： SASAHARA SHOJI
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To improve a branch predicting mechanism by writing a branch profile to directly control the branching tendency by a software. SOLUTION: A microcomputer has a branch predicting device comprising a branch pattern prediction preparing means which operates in advance the branch pattern on a predictable command execution path based on a predetermined branch predicting command by a software, a branch predicting pattern feeding means for fitting the branch predicting pattern from the branch pattern prediction preparing means corresponding to the predetermined branch predicting command generated in executing the actual command and directing feeding it, and a branch prediction executing means for executing the branch prediction based on the branch prediction pattern fed from the branch prediction pattern feeding means.

3. 发明专利

JP2001273137A MICROPROCESSOR 失效
公开(公告)号：JP2001273137A
公开(公告)日：2001-10-05
申请号：JP2000088972
申请日：2000-03-28
申请人： TOSHIBA CORP
发明人： SASAHARA SHOJI
IPC分类号： G06F9/38 , G06F9/42 , G06F12/08
摘要： PROBLEM TO BE SOLVED: To provide a microprocessor capable of suppressing performance decrement due to a cache error when a specific instruction is issued. SOLUTION: This processor is provided with an instruction buffer/queue 1, a performance unit 2, a subroutine call decoder 3, a data cache control unit 4, an Addiu decoder 11 detecting an addiu instruction, a prefetch controlling part 12, an adder 13, a PAdr register 14, a selector 15 and an adder 16. When a subroutine call comes, a stack pointer is moved as much as data to be used in the subroutine, and the data used in the subroutine are prefetched and stored in a subroutine use area in a data cache. Therefore, it is possible to reduce the penalty of the cache error due to stack access that is inclined to occur at a time when the subroutine call is made.

4. 发明专利

JP2001222470A TRANSLATION LOOK ASIDE BUFFER CIRCUIT 失效
公开(公告)号：JP2001222470A
公开(公告)日：2001-08-17
申请号：JP2001010267
申请日：2001-01-18
申请人： TOSHIBA CORP
发明人： SASAHARA SHOJI
IPC分类号： G06F9/355 , G06F12/08 , G06F12/10
摘要： PROBLEM TO BE SOLVED: To speed up conversion into a physical address and the judgment of a cache hit. SOLUTION: A DTLB in a microprocessor of this invention is provided with an adder for adding a base address and a code-extended offset address, a comparator for judging whether the upper twenty bits [31:12] of the base address coincide with the base address stored in an upper address storing part in a CAM 35 and whether the upper four bits of an offset address coincide with an offset address stored in the CAM 35 or not, a comparator for judging whether a carry signal outputted from the adder coincides with a carry signal stored in a carry storing part in the CAM 35, and a coincidence detection part for outputting a coincidence signal when the comparison results of both the comparators coincide. Since the coincidence/-non-coincidence of the lower twelve bits of a virtual address is judged only by a carry signal, the coincidence/non- coincidence of the virtual address can be judged before completing the addition processing of the adder.

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