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1. 发明专利

JP2009110032A Bridge, information processor, information processing system, and global address management method 审中-公开
标题翻译：桥梁，信息处理器，信息处理系统和全球地址管理方法
公开(公告)号：JP2009110032A
公开(公告)日：2009-05-21
申请号：JP2006008004
申请日：2006-01-16
申请人： Sony Computer Entertainment Inc , Sony Corp , ソニー株式会社 , 株式会社ソニー・コンピュータエンタテインメント
发明人： YAMAZAKI TAKESHI , SAITO HIDEYUKI , TAKAHASHI YUJI , MITSUHAYASHI HIDEKI
IPC分类号： G06F15/17 , G06F13/14 , G06F13/36
CPC分类号： H04L29/12367 , H04L61/2514
摘要： PROBLEM TO BE SOLVED: To provide the transparency of resources between nodes on a computer network. SOLUTION: In an information processing system composed of a plurality of processor units connected to each other by a switching apparatus, a global address space having a map of the effective addresses of the processor units and shared between the processor units is introduced. A bridge for relaying the input/output bus of each processor unit to the input/output bus of the switching apparatus receives an access request packet having the effective address of a target node from the processor unit, converts the effective address of the target node into a global address by adding the node identification number necessary for switching of the target node to the effective address, and outputs the access request packet having the global address to the switching apparatus. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供计算机网络上的节点之间的资源的透明度。解决方案：在由交换装置彼此连接的多个处理器单元组成的信息处理系统中，引入具有处理器单元的有效地址并在处理器单元之间共享的映射的全局地址空间。用于将每个处理器单元的输入/输出总线中继到交换设备的输入/输出总线的桥接器从处理器单元接收具有目标节点的有效地址的接入请求分组，将目标节点的有效地址转换为通过将目标节点切换所需的节点标识号添加到有效地址，并将具有全局地址的访问请求分组输出给切换装置，从而产生全球地址。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009037639A Dmac issue mechanism via streaming identification method 有权
标题翻译： DMAC问题机制通过流行识别方法
公开(公告)号：JP2009037639A
公开(公告)日：2009-02-19
申请号：JP2008260019
申请日：2008-10-06
申请人： Sony Computer Entertainment Inc , 株式会社ソニー・コンピュータエンタテインメント
发明人： KING MATTHEW E , LIU PEICHUN PETER , MUI DAVID , YAMAZAKI TAKESHI
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/3625
摘要： PROBLEM TO BE SOLVED: To provide a method and/or a device for making a DMAC-issuing mechanism efficient.
SOLUTION: A direct memory access request command-issuing system 100 uses a streaming ID from a processing element. The issuing system 100 has a bus 130, a memory controller 122 and bus interface units 116, 118 and 120. The BIU means are connected between the bus means and the DMAC means. The memory controller 122 determines what command is developed as a command bus request. The determination is made as the function of an issuing policy which takes, as a factor, at least one selected from slot alteration, a streaming ID and a new or old command.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种使DMAC发布机制有效的方法和/或设备。解决方案：直接存储器访问请求命令发布系统100使用来自处理元件的流ID。发行系统100具有总线130，存储器控制器122和总线接口单元116,118和120.BIU装置连接在总线装置和DMAC装置之间。存储器控制器122确定什么命令被开发为命令总线请求。确定作为发布策略的功能，其作为因素选择从时隙更改，流ID和新旧命令中选择的至少一个。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2007179563A Method of optimizing graphics processing 有权
标题翻译：优化图形处理的方法
公开(公告)号：JP2007179563A
公开(公告)日：2007-07-12
申请号：JP2007035802
申请日：2007-02-16
申请人： Sony Computer Entertainment Inc , 株式会社ソニー・コンピュータエンタテインメント
发明人： SASAKI NOBUO , YAMAZAKI TAKESHI
IPC分类号： G06T11/00 , G06F9/50 , G06T1/20 , G06T11/40 , G06T15/00 , G09G5/393
CPC分类号： G06F9/5083 , G06F9/5066 , G06F2209/501 , G06T1/20 , G06T15/005 , G06T2210/52 , G09G5/393 , G09G2360/121
摘要： PROBLEM TO BE SOLVED: To provide a method for optimizing graphics processing for a multi processor system. SOLUTION: A system comprises geometry processors 502, 504, 506 and graphics processors 508, 510, 512. A communication channel 514 permits communication between the geometry and graphics processors. A control processor 524 may communicate with the geometry and graphics processors through the communication channel. A method of processing graphics data in a computer system is provided to determine whether the geometry and graphics processors are being efficiently utilized. If necessary, one or more of the geometry and graphics processors are selectively assigned or unassigned to improve the efficiency of a graphics processing circuit in performing graphics task. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于优化多处理器系统的图形处理的方法。解决方案：系统包括几何处理器502,504,506和图形处理器508,510,512。通信信道514允许几何图形处理器和图形处理器之间的通信。控制处理器524可以通过通信信道与几何图形处理器通信。提供了一种在计算机系统中处理图形数据的方法，以确定几何图形处理器是否被有效利用。如果需要，一个或多个几何图形处理器被选择性地分配或未分配，以提高图形处理电路在执行图形任务时的效率。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007072616A Shared memory device 有权
标题翻译：共享内存设备
公开(公告)号：JP2007072616A
公开(公告)日：2007-03-22
申请号：JP2005257074
申请日：2005-09-05
申请人： Sony Computer Entertainment Inc , Sony Corp , ソニー株式会社 , 株式会社ソニー・コンピュータエンタテインメント
发明人： KASHIWATANI MOTOFUMI , YAMAZAKI TAKESHI , HAYASHI HIROSHI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16 , G06F15/167 , H01L21/82
CPC分类号： G11C5/025 , G11C7/10 , G11C7/1006
摘要： PROBLEM TO BE SOLVED: To provide a shared memory device capable of simplifying wiring to memory, preventing performance degradation due to an increase in area and long-distance wiring, and increasing the speed of memory access. SOLUTION: The input/output port 211 of a processing module 21, memory interfaces 222, 232, and memory banks 221-1 to 221-n, 231-1 to 231-n are interconnected by connection wiring arranged in the form of a matrix (grid) in Y-direction (first direction) and in X-direction (second direction) in the (upper layer of) layout area of a plurality of memory macros 221, 231. The connection wiring comprises indication information wiring (command address wiring) and data wiring (write wiring and read wiring or common wiring) arranged in multiple layers. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够简化对存储器的布线的共享存储器件，防止由于面积增加和长距离布线引起的性能劣化，并提高存储器访问速度。解决方案：处理模块21，存储器接口222,232和存储体221-1至221-n，231-1至231-n的输入/输出端口211通过布置成形式的连接布线互连在多个存储宏221,223的（上层）布局区域中的Y方向（第一方向）和X方向（第二方向）上的矩阵（栅格）。连接布线包括指示信息布线命令地址布线）和数据布线（写入布线和读取布线或公共布线）。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2007036223A Method and device for designing module 审中-公开
标题翻译：用于设计模块的方法和设备
公开(公告)号：JP2007036223A
公开(公告)日：2007-02-08
申请号：JP2006191471
申请日：2006-07-12
申请人： Internatl Business Mach Corp , Sony Computer Entertainment Inc , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation , 株式会社ソニー・コンピュータエンタテインメント
发明人： KAHLE JAMES ALLAN , HARM PETER HOFSTEE , YAMAZAKI TAKESHI
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5045
摘要： PROBLEM TO BE SOLVED: To suppress the redesign time of a chip in chip designing to a minimum. SOLUTION: Disclose is a method of providing a custom design chip, without redesigning a module that includes design, in variable and scalable designing of a modular multiprocessor. A PU module, a first plurality of assist processing modules and a first plurality of DMA control modules, each being associated with different one of the plurality of assist processing modules are involved in this designing. A first multiprocessor design is created, including at least one module from among the plurality of modules, and the number of modules to be deleted and/or added is preliminarily selected from the first design. Furthermore, a second multiprocessor design is performed with preliminarily selected modules of the selected number deleted therefrom and/or are added thereto. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：将芯片设计中的芯片的重新设计时间抑制到最小。解决方案：Disclose是一种在模块化多处理器的可变和可扩展设计中提供定制设计芯片的方法，而无需重新设计包含设计的模块。在该设计中涉及PU模块，第一多个辅助处理模块和第一多个DMA控制模块，每个都与多个辅助处理模块中的不同的一个相关联。创建第一多处理器设计，包括来自多个模块中的至少一个模块，并且从第一设计中预先选择要删除和/或添加的模块的数量。此外，使用从其中删除的选定号码的预先选择的模块和/或添加到第二多处理器设计来执行第二多处理器设计。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006318477A Method and apparatus for resource management in logically partitioned processing environment 有权
标题翻译：物流处理环境资源管理方法与装置
公开(公告)号：JP2006318477A
公开(公告)日：2006-11-24
申请号：JP2006133249
申请日：2006-05-12
申请人： Internatl Business Mach Corp , Sony Computer Entertainment Inc , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation , 株式会社ソニー・コンピュータエンタテインメント
发明人： YAMAZAKI TAKESHI , HORIKAWA TSUTOMU , MURATA KENICHI , DAY MICHAEL NORMAN
IPC分类号： G06F9/46 , G06F9/50 , G06F12/08 , G06F12/12
CPC分类号： G06F9/5077 , G06F9/5016 , G06F12/084 , G06F12/0842 , G06F12/12 , G06F2209/504 , Y02D10/22
摘要： PROBLEM TO BE SOLVED: To combine aspects of logical partitioning of a processing system with resource management, in terms of resource consumption. SOLUTION: Methods and apparatus are provided for logically partitioning respective processors 102 of a multi-processing system 100 into a plurality of resource groups and time-allocating resources among the resource groups as the function of a predetermined algorithm. The resources include at least one of: (i) allocated portions of communication bandwidths between the processors 102 and one or more input/output devices 110; (ii) allocated portions of space within a shared memory 106 used by the processors 102; and (iii) sets of cache memory lines used by the processors 102. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在资源消耗方面，将处理系统的逻辑分区与资源管理相结合。提供了用于将多处理系统100的各个处理器102逻辑划分为资源组中的多个资源组和时间分配资源的方法和装置，作为预定算法的函数。资源包括以下至少一个：（i）分配处理器102与一个或多个输入/输出设备110之间的通信带宽的部分; （ii）在处理器102使用的共享存储器106内分配的空间部分; 和（iii）处理器102使用的一组高速缓存存储器线。版权所有：（C）2007，JPO＆INPIT

7. 发明专利

JP2006286002A System and device for performing consistency management in distributed type multiprocessor system 有权
标题翻译：在分布式多处理器系统中执行一致性管理的系统和设备
公开(公告)号：JP2006286002A
公开(公告)日：2006-10-19
申请号：JP2006102826
申请日：2006-04-04
申请人： Internatl Business Mach Corp , Sony Computer Entertainment Inc , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation , 株式会社ソニー・コンピュータエンタテインメント
发明人： YAMAZAKI TAKESHI , BROWN JEFFREY D , CLARK SCOTT D , JOHNS CHARLES RAY
IPC分类号： G06F15/17 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/251 , G06F2212/253
摘要： PROBLEM TO BE SOLVED: To perform data consistency management required in some conditions for sharing data. SOLUTION: By means of this method/device, the following steps are provided steps for: transmitting a data command from one device among a plurality of devices to a second address concentration part AC1B inside one processor system 100B among a plurality of processor systems 100; selecting one processor system 100A, which is another processor system storing data transmitted by the data command in itself; transmitting the data command to a first address concentration part AC0A of the selected processor system 100A; and broadcasting the data command from the first address concentration part AC0A of the selected processor system 100A to the second address concentration part AC1 included in each of a plurality of processor systems 100. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在某些条件下执行数据一致性管理以共享数据。解决方案：通过该方法/设备，提供以下步骤：将多个设备中的一个设备的数据命令从多个处理器中的一个处理器系统100B内的第二地址集中部分AC1B发送到多个处理器系统100; 选择一个处理器系统100A，其是存储由数据命令本身发送的数据的另一个处理器系统; 将所述数据命令发送到所选择的处理器系统100A的第一地址集中部分AC0A; 并将数据命令从所选择的处理器系统100A的第一地址集中部分AC0A广播到包括在多个处理器系统100中的每个处理器系统100中的第二地址浓度部分AC1。（C）2007，JPO＆INPIT

8. 发明专利

JP2006221645A Method and device for synchronizing data access to local memory in multiprocessor system 有权
标题翻译：用于同步数据访问多处理器系统中的本地存储器的方法和设备
公开(公告)号：JP2006221645A
公开(公告)日：2006-08-24
申请号：JP2006029780
申请日：2006-02-07
申请人： Sony Computer Entertainment Inc , 株式会社ソニー・コンピュータエンタテインメント
发明人： YAMAZAKI TAKESHI
IPC分类号： G06F15/17 , G06F12/06
CPC分类号： G06F15/167
摘要： PROBLEM TO BE SOLVED: To increase the speed for processing data access. SOLUTION: A management processor 102B receives a request from a starting device 116, which starts data transfer to a local memory 104A, in order to execute one or more programs. The local memory 104A operates together with one of a plurality of parallel processors which can communicate with a shared memory. When completing data transfer to the local memory 104A, a synchronous signal showing completion of data transmission of data to the local memory 104A is generated. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提高处理数据访问的速度。解决方案：管理处理器102B从启动设备116接收请求，该启动设备开始数据传送到本地存储器104A，以执行一个或多个程序。本地存储器104A与可以与共享存储器通信的多个并行处理器中的一个一起操作。当完成向本地存储器104A的数据传送时，产生表示数据向本地存储器104A的数据传输完成的同步信号。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2006190301A Method and device for information processing 有权
标题翻译：用于信息处理的方法和装置
公开(公告)号：JP2006190301A
公开(公告)日：2006-07-20
申请号：JP2006000923
申请日：2006-01-05
申请人： Sony Computer Entertainment Inc , 株式会社ソニー・コンピュータエンタテインメント
发明人： YAMAZAKI TAKESHI , HORIKAWA TSUTOMU , KAHLE JAMES A , JOHNS CHARLES RAY , DAY MICHAEL N , PEICHUN PETER RYUU
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , Y02D10/14
摘要： PROBLEM TO BE SOLVED: To efficiently perform data transfer between a shared memory and a local memory. SOLUTION: In an information processor, the processor 102 can communicate with the shared memory 106, and a direct-memory-access controller (DMAC) 160 can be connected with the local memory 104. According to one DMA command issued by the processor 102 to the DMAC, a plurality of data blocks are transferred between the shared memory 106 and the local memory 104. COPYRIGHT: (C)2006,JPO&NCIPI

10. 发明专利

JP2005310166A Multiscalar expansion to simd instruction set processor 有权
标题翻译： SIMD指令集处理器的多功能扩展
公开(公告)号：JP2005310166A
公开(公告)日：2005-11-04
申请号：JP2005125339
申请日：2005-04-22
申请人： Sony Computer Entertainment Inc , 株式会社ソニー・コンピュータエンタテインメント
发明人： YAMAZAKI TAKESHI
IPC分类号： G06F9/38 , G06F9/30 , G06F15/00 , G06F15/80
CPC分类号： G06F9/30101 , G06F9/3851 , G06F9/3867 , G06F9/3885 , G06F9/3887
摘要： PROBLEM TO BE SOLVED: To impart a multiscalar execution function to a SIMD instruction set processor.
SOLUTION: A method for executing the sequence of a plurality of instructions allowing parallel execution by the processor 110 having a plurality of execution units operated by a single instruction unit includes (a) detecting the sequence of the plurality of instructions applied for the parallel execution from an instruction transmitted to the processor 110, and each the sequence is applied for execution by a subset of the plurality of execution units 112-142. The method includes (b) recording information showing a stall state of the execution unit. Next, step (c) is executed, wherein (i) all of the plurality of execution units except the subset corresponding to the unexecuted sequence is stalled, and (ii) the sequence of the instruction is executed by the corresponding subset, to each the unexecuted sequence among the plurality of sequences.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：向SIMD指令集处理器传递多级执行功能。解决方案：一种用于执行允许具有由单个指令单元操作的多个执行单元的处理器110并行执行的多个指令的序列的方法包括（a）检测应用于所述多个指令的多个指令的序列从发送到处理器110的指令并行执行，并且每个序列被应用于多个执行单元112-142的子集执行。该方法包括（b）记录表示执行单元的失速状态的信息。接下来，执行步骤（c），其中（i）除了未执行的序列之外的子集之外的所有多个执行单元被停止，并且（ii）指令的序列由相应的子集执行，多个序列之间的未执行序列。版权所有（C）2006，JPO＆NCIPI

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