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1. 发明专利

JP2009302564A Ic chip package with directly connected leads 有权
标题翻译：具有直接连接引线的IC芯片包
公开(公告)号：JP2009302564A
公开(公告)日：2009-12-24
申请号：JP2009211270
申请日：2009-09-14
申请人： Siliconix Inc , シリコニックス・インコーポレイテッドSiliconix Incorporated
发明人： KASEM Y MOHAMMED , TSUI ANTHONY C , LUO LIXIONG , HO YUEH-SE
IPC分类号： H01L23/48 , H01L23/495
CPC分类号： H01L24/33 , H01L23/4951 , H01L23/49555 , H01L23/49562 , H01L23/49568 , H01L2224/32245 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device structure which reduces on-state resistance and has superior heat dissipating characteristics. SOLUTION: A semiconductor device includes a semiconductor chip having contact regions on an upper or a bottom surface. Each of first and second lead assemblies is formed from a semi-rigid sheet of conductive material and has a lead assembly contact adhered to one of the separate contact regions, respectively, of the semiconductor chip. Each of the first and second lead assemblies has at least one lead connected to and extending from the lead assembly contact. An encapsulant encloses the semiconductor chip, the lead assembly contact of the first lead assembly, and the lead assembly contact of the second lead assembly. The semiconductor device has low electrical and thermal resistance contributions from the package due to the direct connection of the lead assemblies to the chip. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供降低导通电阻并具有优异的散热特性的半导体器件结构。解决方案：半导体器件包括在上表面或底表面上具有接触区域的半导体芯片。第一引线组件和第二引线组件中的每一个由半刚性导电材料片形成，并且具有分别粘附到半导体芯片的单独接触区域中的一个的引线组件触点。第一和第二引线组件中的每一个具有连接到引线组件触点并从引线组件触点延伸的至少一个引线。密封剂封装半导体芯片，第一引线组件的引线组件触点和第二引线组件的引线组件触点。由于引线组件直接连接到芯片，半导体器件具有来自封装的低和低电阻贡献。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2008199048A Manufacture of high-density trenched dmos using sidewall spacer 有权
标题翻译：使用平台间隔件制造高密度高温DMOS
公开(公告)号：JP2008199048A
公开(公告)日：2008-08-28
申请号：JP2008091980
申请日：2008-03-31
申请人： Siliconix Inc , シリコニックス・インコーポレイテッドSiliconix Incorporated
发明人： HSHIEH FWU-IUAN , HO YUEH-SE , LAN BOSCO , DUN JOWEI
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a trenched DMOS transistor having a deep diffusion region which minimizes a region required to provide the deep body diffusion region having a sufficient depth.
SOLUTION: A first oxide layer is formed on an epitaxial layer, and is patterned to define a deep body area under which the deep body region is formed. Before a second oxide layer is formed, first conductive type diffusion preventive regions are formed in each of the deep body areas. A part of the second oxide layer is removed to expose a central portion of the diffusion preventive region, and it leaves the first oxide layer and an oxide sidewall spacer to cover a periphery of the diffusion preventive region. Second conductive type deep body diffusion is performed, by which the deep body region is formed in an epitaxial region between the sidewall spacers. The periphery of the diffusion preventive region suppresses lateral diffusion of a deep body diffusion portion, without suppressing a diffusion depth remarkably.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有深度扩散区域的沟槽DMOS晶体管，其使得提供具有足够深度的深体扩散区域所需的区域最小化。解决方案：第一氧化物层形成在外延层上，并被图案化以限定形成深体区域的深体区域。在形成第二氧化物层之前，在每个深体区域中形成第一导电型扩散防止区域。去除第二氧化物层的一部分以暴露扩散防止区域的中心部分，并且其离开第一氧化物层和氧化物侧壁间隔物以覆盖扩散防止区域的周边。进行第二导电类型的深体扩散，通过该第二导电型深体扩散，在侧壁间隔件之间的外延区域中形成深体区。扩散防止区域的周边抑制深体扩散部分的横向扩散，而不显着抑制扩散深度。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007281515A Trench type dmos transistor manufactured by relatively small number of masking processes and having thick oxide layer in distal region, and its manufacturing method 审中-公开
标题翻译：通过相对小的掩模过程制造并具有远离区域的厚氧化层制造的TRENCH型DMOS晶体管及其制造方法
公开(公告)号：JP2007281515A
公开(公告)日：2007-10-25
申请号：JP2007168352
申请日：2007-06-27
申请人： Siliconix Inc , シリコニックス・インコーポレイテッドSiliconix Incorporated
发明人： HSHIEH FWU-IUAN , CHANG MIKE F , HO YUEH-SE , OWYANG KING
IPC分类号： H01L21/316 , H01L21/336 , H01L29/06 , H01L29/40 , H01L29/78
CPC分类号： H01L29/407 , H01L29/404 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide a DMOS transistor which is manufactured in the relatively small number of masking processes and improves a process controllability and a stability of a breakdown voltage, and its manufacturing method.
SOLUTION: The trench type DMOS transistor is manufactured by using seven masking processes, and one of the processes defines a p+ type deep main body region and forms an active region of the transistor in which its mask is formed in a LOCOS process. Another masking process defines an insulating oxide layer of a distal region thicker than the active region of the transistor, whereby a contamination of a substrate in a production process is reduced and the process controllability can be improved. Further, a field effect distribution is improved by the thick field oxide layer in the distal region, and an electron avalanche yield voltage can be stably expected.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供以相对较少数量的掩模工艺制造的DMOS晶体管，并且提高了工艺可控性和击穿电压的稳定性及其制造方法。解决方案：通过使用七个掩模工艺制造沟槽型DMOS晶体管，并且其中一个工艺限定了p +型深的主体区域，并且在LOCOS工艺中形成其掩模形成的晶体管的有源区。另一掩蔽工艺限定了远离该晶体管有源区的远端区绝缘氧化层，从而降低了生产过程中衬底的污染，并提高了工艺的可控性。此外，通过远端区域中的厚场氧化物层改善场效应分布，并且可以稳定地期望电子雪崩屈服电压。版权所有（C）2008，JPO＆INPIT

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