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1. 发明专利

JP2005235233A Computer system 有权
标题翻译：电脑系统
公开(公告)号：JP2005235233A
公开(公告)日：2005-09-02
申请号：JP2005083005
申请日：2005-03-23
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SENTER CHERYL , WANG JOHANNES
IPC分类号： G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： PROBLEM TO BE SOLVED: To avoid the occurrence of data error due to dependency and to execute a plurality of instructions out of order in a parallel mode.
SOLUTION: This computer system includes a load store unit 205 adapted to make load requests to a memory system out of order regarding all the instructions in an instruction window and to make store requests in order regarding all the instructions in the instruction window, the load store unit makes the load requests if no address collisions and no write pendings are detected between the plurality of instructions and aligns data on a word boundary returned from a memory properly before it is returned.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了避免由于依赖性引起的数据错误的发生，并且以并行模式执行多个指令乱序。解决方案：该计算机系统包括一个加载存储单元205，该加载存储单元205适于对指令窗口中的所有指令进行与存储器系统的加载请求无关的操作，并且对指令窗口中的所有指令进行存储请求，如果在多个指令之间没有检测到地址冲突并且没有检测到写入挂起，则加载存储单元进行加载请求，并且在返回之前将从存储器返回的字边界上的数据对准。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005353091A Computer system 有权
标题翻译：电脑系统
公开(公告)号：JP2005353091A
公开(公告)日：2005-12-22
申请号：JP2005212306
申请日：2005-07-22
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SENTER CHERYL , WANG JOHANNES
IPC分类号： G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： PROBLEM TO BE SOLVED: To avoid the occurrence of a data error caused by dependency and to execute a plurality of instructions in parallel and in out-of-order. SOLUTION: The system includes an instruction fetch unit and an execution unit for executing instructions in out-of-order. The execution unit includes: a register file 250; a plurality of function units 260 and 262; a first bus 254 for transferring data from the register file to the plurality of function units; second buses 275 and 276 for transferring data from the plurality of function units to the register file; and a load and store unit 205 adapted to make load requests to a memory system in out-of-order for all instructions in an instruction window and to make store requests in order for all the instructions in the instruction window. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了避免由依赖性引起的数据错误的发生，并且并行和无序地执行多个指令。解决方案：系统包括指令提取单元和用于以无序执行指令的执行单元。执行单元包括：寄存器文件250; 多个功能单元260和262; 用于将数据从寄存器文件传送到多个功能单元的第一总线254; 用于将数据从多个功能单元传送到寄存器文件的第二总线275和276; 以及装载和存储单元205，其适于对指令窗口中的所有指令进行无序的存储系统的加载请求，并且为了指令窗口中的所有指令而进行存储请求。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005322269A Computer system 有权
标题翻译：电脑系统
公开(公告)号：JP2005322269A
公开(公告)日：2005-11-17
申请号：JP2005181820
申请日：2005-06-22
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SENTER CHERYL , WANG JOHANNES
IPC分类号： G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： PROBLEM TO BE SOLVED: To perform a plurality of instructions out of order in a parallel mode, avoiding occurrence of data errors due to dependence. SOLUTION: The system includes an instruction fetching unit (106) and an execution unit (107) for carrying out instructions in out-of-order manner. The execution unit comprises a register file, a plurality of functional units, a first bus that transfers data from the register file to the plurality of functional units, a second bus that transfers data from the plurality of functional units to the register file, and a load/store unit which is adapted to make a load request to a memory system in the out-of-order manner in relation to all the instructions in the instruction window and make a store request in the in-order manner in relation to all the instructions in the instruction window. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：以并行模式执行多个指令乱序，避免由于依赖而导致的数据错误的发生。解决方案：该系统包括用于以无序方式执行指令的指令取出单元（106）和执行单元（107）。执行单元包括寄存器文件，多个功能单元，将数据从寄存器文件传送到多个功能单元的第一总线，将数据从多个功能单元传送到寄存器堆的第二总线，以及加载/存储单元，其适于以与所述指令窗口中的所有指令相关的无序方式向存储器系统进行加载请求，并且以所有方式按顺序地进行存储请求指令窗口中的指令。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005216326A Computer system 有权
标题翻译：电脑系统
公开(公告)号：JP2005216326A
公开(公告)日：2005-08-11
申请号：JP2005124391
申请日：2005-04-22
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SENTER CHERYL , WANG JOHANNES
IPC分类号： G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： PROBLEM TO BE SOLVED: To avoid the occurrence of a data error caused by dependency and to execute a plurality of instructions in parallel and out-of-order. SOLUTION: An instruction fetch unit (106) and an execution unit (107) for executing instructions out-of-order are included and the execution unit includes: a register file; a plurality of function units; a first bus for transferring data from the register file to the plurality of function units; a second bus for transferring data from the plurality of function units to the register file; and a load/store unit adapted to make load requests to a memory system out-of-order for all instructions in an instruction window and to make store requests in-order for all the instructions in the instruction window. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了避免由依赖性引起的数据错误的发生，并且并行执行多个指令，并且按顺序执行。解决方案：包括用于执行无序指令的指令获取单元（106）和执行单元（107），并且执行单元包括：寄存器文件; 多个功能单元; 用于将数据从所述寄存器文件传送到所述多个功能单元的第一总线; 用于将数据从所述多个功能单元传送到所述寄存器文件的第二总线; 以及加载/存储单元，其适于对指令窗口中的所有指令进行无序的存储器系统的加载请求，并使指令窗口中的所有指令按顺序存储请求。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2005166046A Computer system 有权
标题翻译：电脑系统
公开(公告)号：JP2005166046A
公开(公告)日：2005-06-23
申请号：JP2004337022
申请日：2004-11-22
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SENTER CHERYL , WANG JOHANNES
IPC分类号： G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： PROBLEM TO BE SOLVED: To execute a plurality of instructions out of order like parallel processing by avoiding the occurrence of a data error due to dependability. SOLUTION: A computer system is disclosed which is composed of an execution unit including an instruction fetch unit and a load store unit 205 adapted to perform a load request to a memory system out of order regarding all of instructions in an instruction window and to perform a store request in order regarding all of the instructions in the instruction window, wherein the load store unit 205 includes an address collision means to perform the load request when no address collisions and no write pendings are detected, an address path 220 adapted to manage a plurality of addresses and a data path 210 constituted so that data returned from a memory system is aligned and returned. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过避免可靠性引起的数据错误的发生，以并行处理的顺序执行多个指令。解决方案：公开了一种计算机系统，其包括执行单元，该执行单元包括指令提取单元和加载存储单元205，所述加载存储单元205适于对指令窗口中的所有指令执行与存储器系统无关的加载请求，为了执行指令窗口中的所有指令的顺序执行存储请求，其中加载存储单元205包括地址冲突装置，用于当没有检测到地址冲突和没有写入挂起时执行加载请求，地址路径220适于管理多个地址和构成为使得从存储器系统返回的数据被对准和返回的数据路径210。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005149525A Computer system 有权
标题翻译：电脑系统
公开(公告)号：JP2005149525A
公开(公告)日：2005-06-09
申请号：JP2004370411
申请日：2004-12-22
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SENTER CHERYL , WANG JOHANNES
IPC分类号： G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： PROBLEM TO BE SOLVED: To execute a plurality of instructions out of order like parallel processing by evading the occurrence of a data error due to dependency.
SOLUTION: A load store unit (205) adapted to make load requests out of order to a memory system in relation to all instructions in an instruction window and to make store requests in order in relation to all the instructions in the instruction window makes a load request, aligns data returned from the memory system, and transfers data on a word boundary when no address collisions or no writing pendings are detected.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过避免依赖性导致的数据错误的发生，以并行处理执行多个指令。解决方案：一种加载存储单元（205），其适于根据指令窗口中的所有指令使存储器系统不合格的加载请求，并且使命令相对于指令窗口中的所有指令进行存储请求进行加载请求，对齐从存储器系统返回的数据，并且当没有检测到地址冲突或没有写入挂起时，在字边界上传送数据。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2006073025A Computer system 有权
标题翻译：电脑系统
公开(公告)号：JP2006073025A
公开(公告)日：2006-03-16
申请号：JP2005274178
申请日：2005-09-21
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SENTER CHERYL , WANG JOHANNES
IPC分类号： G06F9/38 , G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： PROBLEM TO BE SOLVED: To evade the occurrence of a data error due to dependency and to execute a plurality of instructions in a parallel mode in an out-of-order fashion. SOLUTION: A computer system includes an instruction fetch unit and an execution unit for executing the instructions out-of-order. The execution unit includes: a register file (250); a plurality of functional units (260, 262); first buses (254, 225) for transferring data from the register file to the plurality of functional units; second buses (275, 276) for transferring the data from the plurality of functional units to the register file; and a load store unit (205) adapted to make load requests to a memory system out-of-order for all the instructions in an instruction window and store requests in-order for all the instructions in the instruction window. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了避免由于依赖性而导致的数据错误的发生，并且以无序的方式以并行模式执行多个指令。解决方案：计算机系统包括指令提取单元和用于执行无序指令的执行单元。执行单元包括：寄存器文件（250）; 多个功能单元（260,262）; 用于将数据从所述寄存器文件传送到所述多个功能单元的第一总线（254,225）用于将数据从多个功能单元传送到寄存器文件的第二总线（275,276）以及加载存储单元（205），其适于对指令窗口中的所有指令进行无序的存储器系统的加载请求，并且按顺序存储请求指令中的所有指令的请求。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2006048713A Computer system 有权
标题翻译：电脑系统
公开(公告)号：JP2006048713A
公开(公告)日：2006-02-16
申请号：JP2005239264
申请日：2005-08-22
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SENTER CHERYL , WANG JOHANNES
IPC分类号： G06F9/38 , G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： PROBLEM TO BE SOLVED: To perform a plurality of instructions in parallel mode in an out-of-order by avoiding occurrence of data errors due to dependence. SOLUTION: This computer system includes an instruction fetching unit and an execution unit for carrying out instructions in the out-of-order manner, the execution unit carries out a load request of a memory system in the out-of-order manner, in relation to a register file (250), a plurality of functional units (260, 262), a first bus (254, 225) which transmits data from a register file to a plurality of functional units, a second bus (270, 275, 276) which transfers the data from the plurality of functional units to the register file and all the instructions in an instruction window and a load store unit (205) adapted to carry out a store request in an in-order manner, in relation to all the instructions in the instruction window. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过避免由于依赖而导致的数据错误的发生，以并行模式执行多个指令。解决方案：该计算机系统包括指令取出单元和用于以无序方式执行指令的执行单元，执行单元以无序方式执行存储器系统的加载请求关于寄存器文件（250），多个功能单元（260,262），将数据从寄存器文件发送到多个功能单元的第一总线（254,225），第二总线（270， 275，276），其将数据从多个功能单元传送到寄存器文件以及指令窗口中的所有指令和适于以按顺序执行存储请求的加载存储单元（205）到指令窗口中的所有说明。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005243050A Computer system 有权
标题翻译：电脑系统
公开(公告)号：JP2005243050A
公开(公告)日：2005-09-08
申请号：JP2005148862
申请日：2005-05-23
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SENTER CHERYL , WANG JOHANNES
IPC分类号： G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： PROBLEM TO BE SOLVED: To execute a plurality of instructions in a parallel processing manner by out-of-order by avoiding the occurrence of a data error due to dependence. SOLUTION: A computer system includes an instruction fetch unit (106) and an execution unit (107) for executing an instruction by out-of-order. The execution unit includes: a register file; a plurality of functional units; a first bus for transferring data from the register file to the plurality of functional units; a second bus for transferring data from the plurality of functional units to the register file; and a load store unit adapted so as to make a load request to a memory system for all instructions in an instruction window by out-of-order and make a store request for all of the instructions in the instruction window by in-order. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过避免由于依赖性而导致的数据错误的发生，以并行处理方式执行多个指令。解决方案：计算机系统包括用于通过无序执行指令的指令获取单元（106）和执行单元（107）。执行单元包括：寄存器文件; 多个功能单元; 用于将数据从所述寄存器文件传送到所述多个功能单元的第一总线; 用于将数据从所述多个功能单元传送到所述寄存器文件的第二总线; 以及加载存储单元，其适于使得通过无序的方式向指令窗口中的所有指令对存储器系统进行加载请求，并且通过按顺序对所述指令窗口中的所有指令进行存储请求。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2005174364A Computer system 有权
标题翻译：电脑系统
公开(公告)号：JP2005174364A
公开(公告)日：2005-06-30
申请号：JP2005013797
申请日：2005-01-21
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SENTER CHERYL , WANG JOHANNES
IPC分类号： G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： PROBLEM TO BE SOLVED: To perform a plurality of instructions in parallel mode in an out-of-order manner, by avoiding occurrence of data errors due to dependence. SOLUTION: The system includes an instruction fetching unit and an execution unit for carrying out instructions in the out-of-order manner. The execution unit carries out a load request of a memory system in the out-of-order manner, in relation to all the instructions in an instruction window. A load store unit adapted so that it is suited to a store request in an in-order manner, in relation to all the instructions in the instruction window carries out the load request, when address collisions and writing pendings are not detected among the plurality of instructions. When the address collision is detected, an address related to the instructions is managed by an address path 220. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过避免由于依赖性而导致的数据错误的发生，以无序的方式执行并行模式的多个指令。解决方案：系统包括指令取出单元和用于以无序方式执行指令的执行单元。执行单元相对于指令窗口中的所有指令以无序的方式执行存储器系统的加载请求。一种加载存储单元，适于使其适合于按顺序的存储请求，关于指令窗口中的所有指令执行加载请求，当在多个存储单元中未检测到地址冲突和写入挂接说明。当检测到地址冲突时，与指令相关的地址由地址路径220管理。版权所有（C）2005，JPO＆NCIPI

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