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1. 发明专利

JP2006270329A Data transfer controller and electronic equipment 有权
标题翻译：数据传输控制器和电子设备
公开(公告)号：JP2006270329A
公开(公告)日：2006-10-05
申请号：JP2005083540
申请日：2005-03-23
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HONDA HIROYASU
IPC分类号： H04L13/08 , H04L12/40
CPC分类号： G09G5/006 , G09G3/3611
摘要： PROBLEM TO BE SOLVED: To provide a data transfer controller capable of achieving highly efficient serial transfer, and to provide electronic equipment that includes the same. SOLUTION: The data transfer controller includes a link controller 100 for analyzing a packet, received via a serial bus, a packet detection circuit 312 for detecting the end of reception or the start of reception of the packet, on the basis of the analysis results of the received packet, first/second packet buffers 301, 302 into which the packet received via the serial bus is written, and a switching circuit 303 for executing the switching control of writing destinations of the received packet. The switching circuit 303 switches the writing destination of a (K+1)-th packet to the other packet buffer when a K-th packet is written into one of the first/second packet buffers 301, 302 and the end of the reception of the K-th packet or the start of the reception of the (K+1)-th packet is detected. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够实现高效串行传输的数据传输控制器，并提供包括该数据传输控制器的电子设备。解决方案：数据传输控制器包括用于分析经由串行总线接收的分组的链路控制器100，用于检测分组的结束或开始接收分组的分组检测电路312 写入经由串行总线接收的分组的接收分组，第一/第二分组缓冲器301,302的分析结果以及用于执行对所接收分组的写入目的地的切换控制的切换电路303。当第K个分组被写入第一/第二分组缓冲器301,302中的一个和接收的结束时，切换电路303将第（K + 1）个分组的写入目的地切换到另一个分组缓冲器检测第K个分组或第（K + 1）个分组的接收的开始。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2006267379A Data transfer controller and electronic apparatus 有权
标题翻译：数据传输控制器和电子设备
公开(公告)号：JP2006267379A
公开(公告)日：2006-10-05
申请号：JP2005083541
申请日：2005-03-23
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HONDA HIROYASU
IPC分类号： G09G5/00 , G09G3/20 , G09G3/36
CPC分类号： G09G5/006 , G09G2370/04 , H04J3/0632 , H04L12/56 , H04L12/64
摘要： PROBLEM TO BE SOLVED: To provide a data transfer controller capable of efficiently transmitting a vertical synchronizing signal outputted from a display driver to an opposite party device and an electronic apparatus including the data transfer controller. SOLUTION: The data transfer controller comprises: a link controller 100 for analyzing a packet received via a serial bus and generating a packet to be transmitted via the serial bus; an interface circuit 110 for executing interface processing with a display driver 6 connected via an interface bus; and a signal detection circuit 360 for detecting a vertical synchronizing signal VCIN for notifying the non-display period of a display panel and outputting a detection signal VDET. When a read request packet requesting the reading of status of a VCIN is received, the link controller 100 waits for the output of a VDET, and under a condition that the VDET is output, transmits a response packet via the serial bus. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种数据传输控制器，其能够将从显示驱动器输出的垂直同步信号有效地发送到对方设备和包括数据传送控制器的电子设备。数据传输控制器包括：链路控制器100，用于分析经由串行总线接收的分组，并产生要通过串行总线发送的分组; 接口电路110，用于通过经由接口总线连接的显示驱动器6执行接口处理; 以及用于检测用于通知显示面板的非显示周期并输出检测信号VDET的垂直同步信号VCIN的信号检测电路360。当接收到请求读取VCIN的状态的读取请求包时，链路控制器100等待输出VDET，并且在输出VDET的条件下经由串行总线发送响应分组。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007179572A Data transfer controller and electronic apparatus 有权
标题翻译：数据传输控制器和电子设备
公开(公告)号：JP2007179572A
公开(公告)日：2007-07-12
申请号：JP2007069414
申请日：2007-03-16
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HONDA HIROYASU
IPC分类号： G06F13/38
CPC分类号： Y02D10/14 , Y02D10/151
摘要： PROBLEM TO BE SOLVED: To provide a data transfer controller and electric apparatus for efficiently transferring data in various formats serially while suppressing an increase in a scale of a circuit. SOLUTION: The data transfer control device includes an interface circuit 92 for performing interface processing with a host device 5 connected through a system bus, and a link controller 90 for analyzing a packet received through a serial bus, and outputting data having data unit of K bits to the interface circuit 92. Packetized data, which is (N×I)-byte data generated by gathering M pieces of (K+L)-bit data obtained by adding L-bit dummy data to the K-bit data, wherein L and M are variably set depending on K, is inserted in a data field of the received packet through the serial bus. The link controller 90 includes a data formatter 300 for extracting the K-bit data from the packetized data and outputting to the interface circuit 92. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种数据传输控制器和电气设备，用于在抑制电路规模的增加的同时，以串行方式有效地传输数据。数据传输控制装置包括用于通过系统总线连接的主机装置5执行接口处理的接口电路92和用于分析通过串行总线接收的分组并且输出具有数据的数据的链路控制器90 将K位的单位输出到接口电路92.分组化数据是（N×I）字节数据，通过收集通过将L位伪数据加到K位而获得的（K + L）位数据其中L和M根据K可变地设置的数据通过串行总线插入到接收到的分组的数据字段中。链路控制器90包括用于从打包数据中提取K位数据并输出到接口电路92的数据格式化器300.（C）2007，JPO＆INPIT

4. 发明专利

JP2005260066A Flexible substrate and electronic apparatus 有权
标题翻译：柔性基板和电子设备
公开(公告)号：JP2005260066A
公开(公告)日：2005-09-22
申请号：JP2004070990
申请日：2004-03-12
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： FUJIMORI KEITARO , NONOYAMA MIHIRO , SHIBATA YUKINARI , ONO YOSHITERU , HONDA HIROYASU , IWASA YOSHIROU
IPC分类号： H05K1/02 , G06F3/14 , G09G5/00 , H01L23/538 , H01L23/66 , H01L25/18 , H03F3/45 , H05K1/00 , H05K1/14 , H05K1/18
CPC分类号： H01L25/18 , G06F3/14 , G06F3/1423 , G09G5/006 , H01L23/5387 , H01L23/66 , H01L2223/6627 , H01L2223/6638 , H01L2224/16 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/1903 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K1/0237 , H05K1/0393 , H05K1/148 , H05K1/189 , H05K2201/0715 , H05K2201/09236 , H05K2201/09727 , Y10S370/912 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a flexible substrate having excellent cost performance capable of suppressing signal reflection at the time of transmitting a high frequency and capable of performing high-speed serial data transfer while reducing signal deterioration, and an electronic apparatus including the flexible substrate. SOLUTION: The flexible substrate 10 comprises a 1st AR1 provided with a 1st device DV1, a 2nd AR2 provided with a 2nd device DV2 and wiring AR3 formed between the 1st AR1 and the 2nd AR2, and provided with a plurality of wires for connecting the 1st device DV1 and the 2nd device DV2 to each other. The 1st device DV1 includes at least a 1st data transfer control device 100, and the 2nd device DV2 includes at least a 2nd data transfer control device 200 . The 1st and 2nd data transfer control devices 100, 200 perform data transfer by using differential signals. At least one paired differential signal line DSP using the differential signals is included in the plurality of wires for connecting the 1st device DV1 and the 2nd device DV2 to each other. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种柔性基板，具有优异的成本性能，能够抑制在发送高频时的信号反射并且能够在降低信号劣化的同时执行高速串行数据传输;以及电子设备包括柔性基板。解决方案：柔性基板10包括设置有第一装置DV1的第一AR1，设置有第二装置DV2的第二AR2和形成在第一AR1和第二AR2之间的布线AR3，并且设置有多条电线将第一设备DV1和第二设备DV2相互连接。第一设备DV1至少包括第一数据传输控制设备100，第二设备DV2至少包括第二数据传输控制设备200。第一和第二数据传送控制装置100,200通过使用差分信号执行数据传送。在用于将第一设备DV1和第二设备DV2彼此连接的多条线路中包括使用差分信号的至少一个成对的差分信号线DSP。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2005258579A Data transfer controller and electronic device 有权
标题翻译：数据传输控制器和电子设备
公开(公告)号：JP2005258579A
公开(公告)日：2005-09-22
申请号：JP2004066064
申请日：2004-03-09
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HONDA HIROYASU
IPC分类号： G06F3/153 , G06F5/00 , G06F13/38 , G09G3/20 , G09G3/36 , H04B1/00 , H04L7/08 , H04L25/02
CPC分类号： G06F3/1431 , G06F2213/0038 , G09G5/006 , G09G5/12 , G09G2370/10
摘要： PROBLEM TO BE SOLVED: To provide a data transfer controller capable of reproducing a synchronous signal by simple processing and an electronic device including the controller. SOLUTION: The data transfer controller 30 includes a link controller 100 analyzing a packet received from the data transfer controller 10 at a host side via a serial bus, an interface circuit 110 generating an interface signal and outputting it to an interface bus. The packet transferred from the data transfer controller 10 at the host side via the serial bus includes a synchronous signal code field for setting up synchronous signal code. The interface circuit 110 generates synchronous signals FPFRAME and FPLINE included in the interface signal on the basis of the synchronous signal code provided in the packet. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够通过简单处理再现同步信号的数据传送控制器和包括控制器的电子设备。解决方案：数据传输控制器30包括链路控制器100，该链路控制器100通过串行总线分析从主机侧从数据传输控制器10接收到的分组，接口电路110产生接口信号并将其输出到接口总线。经由串行总线从主机侧的数据传送控制器10传送的数据包包括用于设置同步信号码的同步信号码字段。接口电路110基于分组中提供的同步信号码，生成包含在接口信号中的同步信号FPFRAME和FPLINE。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005258575A Data transfer controller and electronic device 有权
标题翻译：数据传输控制器和电子设备
公开(公告)号：JP2005258575A
公开(公告)日：2005-09-22
申请号：JP2004066029
申请日：2004-03-09
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HONDA HIROYASU
IPC分类号： G06F13/36 , G06F13/38 , H04B1/00 , H04L25/02 , H04L29/06
CPC分类号： G06F3/1423 , G09G3/2092 , G09G3/2096 , G09G5/003 , G09G5/006 , G09G2310/08 , G09G2370/045 , G09G2370/047 , G09G2370/10 , Y10S370/912
摘要： PROBLEM TO BE SOLVED: To provide a data transfer controller capable of flexibly dealing with various interfaces of connected devices and an electronic device including the controller. SOLUTION: The data transfer controller 30 includes a link controller 40 analyzing a packet received from the data transfer controller 10 at a host side via a serial bus, an interface circuit 110 generating an interface signal and outputting it to an interface bus, and an internal register 350 setting up interface information to specify a signal type of the interface signal outputted from the interface circuit 110. The interface circuit 110 includes first to Nth interface circuits 310, 320, and 330 generating interface signals of the signal types following the interface information which is specified with the internal register 350. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够灵活地处理连接的设备的各种接口的数据传输控制器和包括控制器的电子设备。解决方案：数据传输控制器30包括链路控制器40，其通过串行总线分析从主机侧从数据传输控制器10接收到的分组，接口电路110生成接口信号并将其输出到接口总线，以及设置接口信息以指定从接口电路110输出的接口信号的信号类型的内部寄存器350.接口电路110包括第一至第N接口电路310,320和330，其生成跟随在接口电路110上的信号类型的接口信号接口信息由内部寄存器350指定。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2012198288A Integrated circuit device, electro-optical device, and electronic equipment 有权
标题翻译：集成电路设备，电光设备和电子设备
公开(公告)号：JP2012198288A
公开(公告)日：2012-10-18
申请号：JP2011060789
申请日：2011-03-18
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： OGAWA HIDEKI , FUJIMORI KEITARO , HONDA HIROYASU
IPC分类号： G09G3/34 , G02F1/167 , G09G3/20
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit device, an electro-optical device, and electronic equipment that can be each driven with a driving waveform corresponding to environmental information without increasing the capacity of a waveform memory.SOLUTION: An integrated circuit device 100 includes: a driving voltage output section 150 that updates an image of an electro-optical panel; a display data storage section 110 that includes a first storage section 111 storing first display data CI and a second storage section 112 storing second display data NI; a waveform information storage section 120 that stores driving waveform information; driving waveform information output sections 130 and 140 that output, to the driving voltage output section, driving waveform information selected from the waveform information storage section; and an acquiring section 170 that acquires environmental information. Driving waveform information that corresponds to the environmental information acquired by the acquiring section among pieces of driving waveform information respectively corresponding to plural pieces of environmental information sent from a host device 50 is stored in the waveform information storage section.
摘要翻译：要解决的问题：提供一种集成电路器件，电光器件和电子设备，其可以被驱动与对应于环境信息的驱动波形而不增加波形存储器的容量。集成电路装置100包括：更新电光面板的图像的驱动电压输出部150; 显示数据存储部分110，其包括存储第一显示数据CI的第一存储部分111和存储第二显示数据NI的第二存储部分112; 存储驱动波形信息的波形信息存储部120; 驱动波形信息输出部分130和140，其向驱动电压输出部分输出从波形信息存储部分中选择的驱动波形信息; 以及获取部170，其获取环境信息。在波形信息存储部中存储有与从由主机50发送的多条环境信息分别对应的多条驱动波形信息中的与获取部获取的环境信息对应的波形信息。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2012194432A Integrated circuit device, electro-optical device and electronic apparatus 审中-公开
标题翻译：集成电路装置，电光装置和电子装置
公开(公告)号：JP2012194432A
公开(公告)日：2012-10-11
申请号：JP2011059209
申请日：2011-03-17
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HONDA HIROYASU
IPC分类号： G09G3/34 , G02F1/167 , G09G3/20
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit device, etc., capable of receiving display data from a host device without increasing a capacity of a display data memory which is incorporated to the integrated circuit device to be mounted on an electro-optical panel.SOLUTION: An integrated circuit device 100 comprises: a drive voltage output section 150 for updating an image of the electro-optical panel; a display data storage section 110 including a first storage section 111 for storing first display data CI and a second storage section 112 for storing second display data NI to be transmitted from a host device 50; a waveform information storage section 120; drive waveform information output sections 130 and 140 for outputting the drive waveform information to be selected from the waveform information storage section to the drive voltage output section; and a transfer control section 113 for transferring and writing the second display data in the second storage section to the first storge section after a panel image is updated. The drive waveform information output sections make a busy signal A to be active until the image update is finished, such as transfer control in the transfer control section is finished, and the busy signal A is turned to be inactive after the image update is finished.
摘要翻译：解决的问题：提供能够从主机装置接收显示数据的集成电路装置等，而不增加集成到集成电路装置中的显示数据存储器的容量，以安装在电子装置上光盘。解决方案：集成电路装置100包括：用于更新电光面板的图像的驱动电压输出部分150; 显示数据存储部分110，包括用于存储第一显示数据CI的第一存储部分111和用于存储要从主机装置50发送的第二显示数据NI的第二存储部分112; 波形信息存储部120; 驱动波形信息输出部130和140，用于将从波形信息存储部选择的驱动波形信息输出到驱动电压输出部; 以及转印控制部分113，用于在更新面板图像之后将第二显示数据在第二存储部分中传送和写入到第一存储部分。驱动波形信息输出部分使得忙信号A在图像更新完成之前有效，诸如传送控制部分中的传送控制结束，并且在图像更新完成之后，忙信号A变为不活动。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2006268483A Data transfer controller and electronic apparatus 有权
标题翻译：数据传输控制器和电子设备
公开(公告)号：JP2006268483A
公开(公告)日：2006-10-05
申请号：JP2005086187
申请日：2005-03-24
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HONDA HIROYASU
IPC分类号： G06F13/38 , G06F13/36
CPC分类号： H04L12/40117 , G06F13/4045 , H04L69/22 , Y02D10/14 , Y02D10/151
摘要： PROBLEM TO BE SOLVED: To provide a data transfer controller and electronic apparatus that can achieve efficient serial transfer of data in various formats while suppressing an increase in scale of a circuit. SOLUTION: The data transfer controller is provided with an interface circuit 110 to which data having data unit of K bits are inputted through an interface bus and a link controller 100 which generates a packet to be transmitted through a serial bus. The link controller 100 is provided with a data formatter 300 which generates (N×I)-byte packetized data of M pieces of (K+L)-bit data obtained by adding L-bit dummy data to K-bit data and a packet generating circuit 320 which generates a packet having the packetized data inserted into a data field. The data formatter 300 generates packetized data whose L and M are set variably according to K. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种数据传输控制器和电子设备，其可以在抑制电路规模的增加的情况下实现各种格式的数据的有效串行传输。解决方案：数据传输控制器设置有接口电路110，具有通过接口总线输入K位数据单元的数据和产生要通过串行总线发送的分组的链路控制器100。链路控制器100设置有数据格式化器300，其生成通过将L比特伪数据加到K比特数据而获得的M个（K + L）比特数据的（N×I）个字节分组数据，生成电路320，其产生具有插入到数据字段中的分组化数据的分组。数据格式化器300生成根据K可变地设置其L和M的打包数据。（C）2007，JPO＆INPIT

10. 发明专利

JP2006268260A Data transfer controller and electronic equipment 审中-公开
标题翻译：数据传输控制器和电子设备
公开(公告)号：JP2006268260A
公开(公告)日：2006-10-05
申请号：JP2005083539
申请日：2005-03-23
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HONDA HIROYASU
IPC分类号： G06F13/38 , G09G3/20 , G09G3/36 , G09G5/00 , H04L29/08
CPC分类号： H04L7/041 , G09G5/006
摘要： PROBLEM TO BE SOLVED: To provide a data transfer controller capable of preventing trouble etc., due to noises on a serial transmission line and to provide an electronic equipment including the same.
SOLUTION: The data transfer controller is provided with a link controller 100 which analyzes a packet received through a serial bus, an interface circuit 110 which generates and outputs an interface signal to an interface bus, and a reset signal output circuit 312 which outputs a reset signal RST to the interface circuit 110. The link controller 100 analyzes the received packet to determine whether the received packet includes synchronizing signal generation indication information (synchronizing signal code). The reset signal output circuit 312 outputs the reset signal RST to the interface circuit 110 when it is determined that the received packet includes the synchronizing signal generation indication information.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止由串行传输线路上的噪声引起的故障等的数据传送控制器，并提供包括该数据传输控制器的电子设备。解决方案：数据传输控制器设置有链路控制器100，链路控制器100分析通过串行总线接收的分组，接口电路110，其生成并向接口总线输出接口信号;以及复位信号输出电路312，向接口电路110输出复位信号RST。链路控制器100分析接收到的分组，以确定接收的分组是否包括同步信号生成指示信息（同步信号码）。当确定接收到的分组包括同步信号生成指示信息时，复位信号输出电路312将复位信号RST输出到接口电路110。版权所有（C）2007，JPO＆INPIT

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