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1. 发明专利

JP2007201003A Method of manufacturing semiconductor substrate, method of manufacturing semiconductor device, and semiconductor device 审中-公开
标题翻译：制造半导体基板的方法，制造半导体器件的方法和半导体器件
公开(公告)号：JP2007201003A
公开(公告)日：2007-08-09
申请号：JP2006015366
申请日：2006-01-24
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HARA HISAKI
IPC分类号： H01L21/762 , H01L21/02 , H01L21/76 , H01L27/12 , H01L29/786
CPC分类号： H01L21/823481 , H01L21/823418 , H01L21/84 , H01L27/1203
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor substrate which can manufacture a semiconductor substrate so that its size (area) is small, and to provide a method of manufacturing a semiconductor device, and the semiconductor device.
SOLUTION: In the method of manufacturing the semiconductor substrate 41, a first supporter hole 21 and a second supporter hole 22 are first formed on a boundary between a first element isolation layer 12 and an SOI element forming region 13. Then, a supporter forming layer 27 is formed so as to cover the insides of the supporter holes 21, 22 and the top of a silicon layer 16, and after that, a supporter 26 is formed. By forming the first and second supporter holes 21 and 22 on the boundary, the areas of the supporter holes 21, 22 in the SOI element forming region 13 can be reduced.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体衬底的制造方法，该半导体衬底可以制造其尺寸（面积）小的半导体衬底，并提供半导体器件的制造方法和半导体器件。解决方案：在制造半导体基板41的方法中，首先在第一元件隔离层12和SOI元件形成区域13之间的边界上形成第一支撑孔21和第二支撑孔22。支撑体形成层27形成为覆盖支撑孔21,22的内侧和硅层16的顶部，之后形成支撑体26。通过在边界上形成第一和第二支撑孔21和22，可以减少SOI元件形成区域13中的支撑孔21,22的面积。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007103491A Semiconductor device and manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：JP2007103491A
公开(公告)日：2007-04-19
申请号：JP2005288878
申请日：2005-09-30
申请人： Seiko Epson Corp , Tokyo Institute Of Technology , セイコーエプソン株式会社 , 国立大学法人東京工業大学
发明人： KATO JURI , OKA HIDEAKI , KANEMOTO HIROSHI , HARA HISAKI , SAKAI TETSUSHI
IPC分类号： H01L29/786 , H01L21/02 , H01L21/76 , H01L21/762 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To suppress current leak due to a parasitic transistor while suppressing the deterioration of crystallinity of a semiconductor layer on which a field effect transistor is formed.
SOLUTION: An etching gas or an etching liquid is allowed to contact a first semiconductor layer 2 via a groove 8, thereby removing the first semiconductor layer 2 by etching. A cavity portion 9 is formed between a semiconductor substrate 1 and the second semiconductor layer 3, and after that, skew ion implantation IP is performed for a sidewall of the second semiconductor layer 3 via the groove 8, thereby forming an impurity-introducing layer 3a on the sidewall of the second semiconductor layer 3.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了抑制由寄生晶体管引起的电流泄漏，同时抑制形成场效应晶体管的半导体层的结晶性的劣化。解决方案：允许蚀刻气体或蚀刻液通过凹槽8接触第一半导体层2，从而通过蚀刻去除第一半导体层2。在半导体衬底1和第二半导体层3之间形成空腔部分9，然后经由沟槽8对第二半导体层3的侧壁进行偏斜离子注入IP，由此形成杂质引入层3a 在第二半导体层3的侧壁上。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007042877A Semiconductor device and its fabrication process 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2007042877A
公开(公告)日：2007-02-15
申请号：JP2005225582
申请日：2005-08-03
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： KATO JURI , HARA HISAKI , KANEMOTO HIROSHI
IPC分类号： H01L29/786 , H01L21/02 , H01L21/76 , H01L21/762 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To enhance uniformity in thickness of a semiconductor layer formed on an insulator without using an SOI substrate.
SOLUTION: After a support 7 is provided on the sidewall of a trench 6 formed in a P type semiconductor substrate 1, a trench 8 for exposing a second semiconductor layer 3 is formed, etching gas or etching liquid is brought into contact with a first semiconductor layer 2 through the trench 8 to form a cavity 9 between the P type semiconductor substrate 1 and the second semiconductor layer 3, and then the P type semiconductor substrate 1, the second semiconductor layer 3 and the support 7 are thermally oxidized thus forming a buried insulation layer 10 in the cavity 9 between the P type semiconductor substrate 1 and the second semiconductor layer 3.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提高形成在绝缘体上的半导体层的厚度的均匀性，而不使用SOI衬底。解决方案：在形成在P型半导体衬底1中的沟槽6的侧壁上设置支撑件7之后，形成用于暴露第二半导体层3的沟槽8，使蚀刻气体或蚀刻液与通过沟槽8的第一半导体层2，以在P型半导体衬底1和第二半导体层3之间形成空腔9，然后将P型半导体衬底1，第二半导体层3和支撑体7热氧化在P型半导体衬底1和第二半导体层3之间的空腔9中形成掩埋绝缘层10.版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007035701A Semiconductor device and method of manufacturing the semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2007035701A
公开(公告)日：2007-02-08
申请号：JP2005212747
申请日：2005-07-22
申请人： Seiko Epson Corp , Tokyo Institute Of Technology , セイコーエプソン株式会社 , 国立大学法人東京工業大学
发明人： OKA HIDEAKI , KATO JURI , HARA HISAKI , KANEMOTO HIROSHI , SAKAI TETSUSHI
IPC分类号： H01L29/786 , H01L21/76 , H01L23/52 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To form buried oxide films below a semiconductor layer, while improving support strength of the semiconductor layer on which a field effect transistor is formed. SOLUTION: The buried oxide films 12 and 14 are formed so that their widths are smaller than the widths of single-crystal semiconductor layers 13 and 15, and a supporter 18 for supporting the semiconductor layers 13 and 15 on a single-crystal semiconductor substrate 11 is arranged so as to enter in below the semiconductor layers 13 and 15 via the sidewalls of the semiconductor layers 13 and 15. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在改善形成场效应晶体管的半导体层的支撑强度的同时，在半导体层之下形成掩埋氧化膜。解决方案：埋入氧化物膜12和14形成为使得它们的宽度小于单晶半导体层13和15的宽度，并且用于在单晶体上支撑半导体层13和15的支撑体18 半导体衬底11被布置成经由半导体层13和15的侧壁进入半导体层13和15的下方。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2007027231A Method of manufacturing semiconductor device, and semiconductor device 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2007027231A
公开(公告)日：2007-02-01
申请号：JP2005203917
申请日：2005-07-13
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HARA HISAKI
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0653
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a DSOI transistor which can prevent the occurrence of crystal defects during manufacturing without requiring a special manufacturing apparatus, and to provide the semiconductor device.
SOLUTION: First, an SiGe layer 3 is formed on an Si substrate 1, and of the SiGe layer 3, a part sandwiched by a source forming region and a drain forming region is etched to be eliminated, and thus, a trench is formed. Next, an Si layer 10 is formed on the Si substrate 1 so as to bury the trench and cover the SiGe layer 3. Then, the Si layer 10 outside the transistor forming region and the SiGe layer 3 outside thereof are etched and eliminated, thereby exposing the side surface of the SiGe layer 3 along the periphery of the transistor forming region. After that, the SiGe layer 3 is etched and eliminated from the exposed side surface, thereby forming cavity portions 15 below the Si layer 10 of the transistor forming region, and subsequently, forming an SiO
2 film 17 in the cavity portions 15.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造具有DSOI晶体管的半导体器件的方法，该半导体器件可以防止在制造期间发生晶体缺陷而不需要特殊的制造设备，并提供半导体器件。解决方案：首先，在Si衬底1上形成SiGe层3，并且蚀刻SiGe层3，夹在源极形成区域和漏极形成区域之间的部分，以消除沟槽形成了。接下来，在Si衬底1上形成Si层10，以埋入沟槽并覆盖SiGe层3.然后，蚀刻并消除晶体管形成区域外的Si层10和外部的SiGe层3，由此沿着晶体管形成区域的外围暴露SiGe层3的侧表面。之后，将SiGe层3从露出的侧表面蚀刻除去，从而在晶体管形成区域的Si层10的下方形成空腔部分15，然后在其中形成SiO 2 膜17 空腔部分15.版权所有：（C）2007，JPO＆INPIT

6. 发明专利

JP2006278657A Process for fabricating semiconductor device 有权
标题翻译：制造半导体器件的工艺
公开(公告)号：JP2006278657A
公开(公告)日：2006-10-12
申请号：JP2005094775
申请日：2005-03-29
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HARA HISAKI
IPC分类号： H01L21/336 , H01L27/12 , H01L29/786
CPC分类号： H01L27/1203 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/823481 , H01L21/84 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To enhance alignment precision of a device while allowing selective fabrication of an SOI structure on a bulk substrate. SOLUTION: A first semiconductor layer 3a and a second semiconductor layer 4a are formed sequentially in an SOI structure forming region R3 by selective epitaxial growth, a first semiconductor layer 3b and a second semiconductor layer 4b are formed sequentially in a first alignment mark forming region R1, an opening 7 for partially exposing a semiconductor substrate 1 in the SOI structure forming region R3 is formed by etching the semiconductor substrate 1, the second semiconductor layer 4a and the first semiconductor layer 3a using a resist pattern 5 formed with reference to the position of a first alignment mark composed of the first semiconductor layer 3b and the second semiconductor layer 4b as a mask, and then a second alignment mark 6 is formed in an alignment mark forming region R2. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提高器件的对准精度，同时允许在体基板上选择性地制造SOI结构。解决方案：通过选择性外延生长，在SOI结构形成区域R3中依次形成第一半导体层3a和第二半导体层4a，在第一对准标记中依次形成第一半导体层3b和第二半导体层4b 在SOI结构形成区域R3中用于部分曝光半导体衬底1的开口7通过使用形成区域R1形成的抗蚀剂图案5蚀刻半导体衬底1，第二半导体层4a和第一半导体层3a来形成由第一半导体层3b和第二半导体层4b构成的第一对准标记作为掩模的位置，然后在对准标记形成区域R2中形成第二对准标记6。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006253259A Semiconductor device and its fabrication process 有权
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2006253259A
公开(公告)日：2006-09-21
申请号：JP2005064994
申请日：2005-03-09
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HARA HISAKI
IPC分类号： H01L29/786 , H01L21/336 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To enlarge the area of a semiconductor layer being formed on an insulator without employing an SOI substrate.
SOLUTION: After a padding insulation layer 10 is formed in a cavity 9 between a semiconductor substrate 1 and a second semiconductor layer 3 by thermally oxidizing the semiconductor substrate 1 and the second semiconductor layer 3 in the cavity 9 through an opening 7, an opening 7' for exposing the sidewall of the second semiconductor layer 3 around the opening 7 is formed, and after an amorphous semiconductor is formed on a support 5 to fill the opening 7', source/drain layers 25a and 25b are formed on the second semiconductor layer 3 and a padding semiconductor layer 13.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在不使用SOI衬底的情况下扩大在绝缘体上形成的半导体层的面积。解决方案：在通过开口7热氧化空腔9中的半导体衬底1和第二半导体层3之后，在半导体衬底1和第二半导体层3之间的空腔9中形成衬垫绝缘层10之后，形成用于将第二半导体层3的侧壁暴露在开口7周围的开口7'，并且在支撑体5上形成非晶半导体以填充开口7'之后，在漏极层25a和25b上形成源极/漏极层25a和25b 第二半导体层3和填充半导体层13.版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2006253258A Semiconductor substrate, semiconductor device, process for producing semiconductor substrate, and process for fabricating semiconductor device 审中-公开
标题翻译：半导体衬底，半导体器件，用于制造半导体衬底的工艺，以及用于制造半导体器件的工艺
公开(公告)号：JP2006253258A
公开(公告)日：2006-09-21
申请号：JP2005064993
申请日：2005-03-09
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HARA HISAKI
IPC分类号： H01L21/76 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To form a semiconductor layer on an insulator inexpensively while suppressing the generation of particles from the semiconductor layer.
SOLUTION: After a trench 8a for exposing the sidewall of a second semiconductor layer 3 is formed, the sidewall of the second semiconductor layer 3 is heat treated under N
2 gas atmosphere to form a protective film 30 on the sidewall of a second semiconductor layer 3. A trench 8b for exposing a portion of a first semiconductor layer 2 is formed by etching the first semiconductor layer 2 while digging the trench 8a, and a cavity 9 is formed between a semiconductor substrate 1 and the second semiconductor layer 3 by touching etching liquid to the first semiconductor layer 2 through the trenches 8a and 8b and removing the first semiconductor layer 2 by etching.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在绝缘体上廉价地形成半导体层，同时抑制从半导体层产生的颗粒。解决方案：在形成用于暴露第二半导体层3的侧壁的沟槽8a之后，在N气氛气氛下对第二半导体层3的侧壁进行热处理，形成保护膜用于暴露第一半导体层2的一部分的沟槽8b通过在挖掘沟槽8a的同时蚀刻第一半导体层2而形成，并且在半导体衬底1 和第二半导体层3，通过沟槽8a和8b将腐蚀液体接触到第一半导体层2，并通过蚀刻去除第一半导体层2。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2006156842A Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device 有权
标题翻译：制造半导体基板的方法和制造半导体器件的方法
公开(公告)号：JP2006156842A
公开(公告)日：2006-06-15
申请号：JP2004347622
申请日：2004-11-30
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HARA HISAKI
IPC分类号： H01L27/12 , H01L21/76 , H01L21/762 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To inexpensively form a semiconductor layer on an insulator while the confinement of the width of the semiconductor layer which can be formed on an insulating film is alleviated.
SOLUTION: A second semiconductor layer 3 is formed in an epitaxial growth on a first semiconductor layer 2, the dissociation of the engagement of an element which constitutes a first semiconductor layer 2 is performed by irradiating the first semiconductor layer 2 with a laser beam R through a second semiconductor layer 3, after a support 5 is provided in the side wall of a groove 6 formed on the semiconductor substrate 1, a groove 8 into which the second semiconductor layer 3 is exposed is formed, a cavity part 9 is formed between the semiconductor substrate 1 and the second semiconductor layer 3 by bringing etching gas or etchant into contact with the first semiconductor layer 2, the semiconductor substrate 1, the second semiconductor layer 3 and the support 5 are thermally oxidized, thereby forming an oxide film 10 in the cavity part 9 between the semiconductor substrate 1 and the second semiconductor layer 3.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在绝缘体上廉价地形成半导体层，同时可以减少可以形成在绝缘膜上的半导体层的宽度的限制。解决方案：在第一半导体层2上以外延生长形成第二半导体层3，通过用激光照射第一半导体层2来实现构成第一半导体层2的元件的接合解离在形成在半导体基板1上的槽6的侧壁中设置支撑体5之后，形成第二半导体层3露出的槽8，空腔部9为通过使蚀刻气体或蚀刻剂与第一半导体层2，半导体衬底1，第二半导体层3和支撑体5接触来形成在半导体衬底1和第二半导体层3之间，从而形成氧化膜在半导体衬底1和第二半导体层3之间的空腔部分9中。10.权利要求：（C）2006，JPO＆NCIPI

10. 发明专利

JP2006114651A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006114651A
公开(公告)日：2006-04-27
申请号：JP2004299809
申请日：2004-10-14
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： HARA HISAKI
IPC分类号： H01L21/28 , H01L21/8234 , H01L27/088
摘要： PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device having a semiconductor metal alloy layer with uniform and good characteristics. SOLUTION: The manufacturing method of a semiconductor device includes (a) a step of forming a gate insulation layer 20 above a semiconductor layer 10, (b) a step of forming a gate electrode 22 above the gate insulation layer, (c) a step of forming a resist layer in a predetermined region above the semiconductor layer, (d) a step of amorphizing the surface 40 of the semiconductor layer not covered with the resist layer, (e) a step of forming a metal layer 32a above the semiconductor layer, and (f) a step of thermal treatment for reacting the amorphous semiconductor layer with the metal layer. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供具有均匀且良好特性的具有半导体金属合金层的半导体器件的制造方法。解决方案：半导体器件的制造方法包括（a）在半导体层10上形成栅极绝缘层20的步骤，（b）在栅极绝缘层上形成栅电极22的步骤，（c ）在半导体层上方的预定区域形成抗蚀剂层的步骤，（d）使未被抗蚀剂层覆盖的半导体层的表面40非晶化的步骤，（e）在上面形成金属层32a的步骤半导体层，以及（f）使非晶半导体层与金属层反应的热处理步骤。版权所有（C）2006，JPO＆NCIPI

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