专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2011108863A Mounting structure, and electronic device 审中-公开
标题翻译：安装结构和电子设备
公开(公告)号：JP2011108863A
公开(公告)日：2011-06-02
申请号：JP2009262619
申请日：2009-11-18
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： ASAKAWA TATSUHIKO , MIYAGAWA KOICHI
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a mounting structure capable of reducing connection resistance of an electronic component using a resin core bump.
SOLUTION: The mounting structure is adapted to electrically connect the electronic component, and includes a circuit board (first substrate) 21, circuit wiring (first connection portion) 22 provided to the circuit board 21, a TFT substrate (second substrate) 2, driving wiring (second connection portion) 12 provided to the TFT substrate 2, and the resin core bump (connection terminal) 30 for electrically connecting the circuit wiring 22 and driving wiring 12 to each other. The resin core bump 30 includes a resin layer 31 provided in a projecting shape to the circuit board 21 or circuit wiring 22, a conductive layer 33 provided covering at least a part of the resin layer 31 to electrically connect the circuit wiring 22 and driving wiring 12 to each other, and particles 32 contained in the resin layer 31.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够降低使用树脂芯凸块的电子部件的连接电阻的安装结构。
解决方案：安装结构适于电连接电子部件，并且包括电路板（第一基板）21，设置到电路板21的电路布线（第一连接部分）22，TFT基板（第二基板） 2，设置在TFT基板2上的驱动布线（第二连接部分）12和用于将电路布线22和驱动布线12彼此电连接的树脂芯凸起（连接端子）30。树脂芯凸块30包括设置在电路板21或电路布线22上的突起形状的树脂层31，覆盖至少一部分树脂层31的导电层33，以将电路布线22和驱动布线 12，并且包含在树脂层31中的颗粒32.版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2008205293A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008205293A
公开(公告)日：2008-09-04
申请号：JP2007041093
申请日：2007-02-21
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： ASAKAWA TATSUHIKO
IPC分类号： H01L23/12 , H01L21/3205 , H01L23/52
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To enable probe inspection without damaging an external terminal comprising a resin layer and wiring formed on the resin layer. SOLUTION: A semiconductor device has a semiconductor substrate 10. In the semiconductor substrate 10, an integrated circuit 12 is formed and there is an electrode 14 connected to the integrated circuit 12 electrically. The resin layer is formed on the surface of the semiconductor substrate 10, where the electrode 14 is formed. The wiring 40 includes: a connection section 42 positioned on the electrode 14 and connected to the electrode 14 electrically; a terminal section 44 that is positioned on the resin layer and composes the external terminal; and a pad 46 connected to the electrode 14 electrically via the connection and terminal sections 42, 44. The terminal section 44 is positioned between the connection section 42 and the pad 46. On the surface of the pad 46, a step 50, which becomes lower in a direction far from the terminal section 44, is formed. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了使探针检查不损坏包括树脂层的外部端子和形成在树脂层上的布线。解决方案：半导体器件具有半导体衬底10.在半导体衬底10中，形成集成电路12，并且电连接到集成电路12上的电极14。树脂层形成在半导体衬底10的形成有电极14的表面上。布线40包括：连接部分42，定位在电极14上并电连接到电极14; 位于树脂层上并构成外部端子的端子部44; 以及通过连接端子部分42,44电连接到电极14的焊盘46.端子部分44位于连接部分42和焊盘46之间。在焊盘46的表面上形成步骤50，其形成在远离端子部分44的方向上形成。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2012209313A Processing apparatus and pipeline 审中-公开
标题翻译：加工设备和管道
公开(公告)号：JP2012209313A
公开(公告)日：2012-10-25
申请号：JP2011071864
申请日：2011-03-29
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： NEISHI YUZO , ASAKAWA TATSUHIKO , YAMANOI HIROSHI
IPC分类号： H01L21/306 , C23F1/08 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To provide a processing apparatus and the like which perform liquid phase processing more uniformly.SOLUTION: A processing apparatus according to this invention includes: a processing tank having a bottom surface, a side surface continuing into the bottom surface, a first opening continuing into the side surface, and a second opening positioned on the side surface; an introduction part provided at the second opening; a pipeline extending from the introduction part into the processing tank and having a terminal part; and a multiple discharge holes provided at the pipeline. The multiple discharge holes include first discharge holes and second discharge holes, and the second discharge holes are located close to the terminal part side relative to the first discharge holes. An opening area of each first discharge hole is larger than an opening area of each second discharge hole.
摘要翻译：要解决的问题：提供更均匀地进行液相处理的处理装置等。解决方案：根据本发明的处理装置包括：处理罐，其具有底表面，连续进入底表面的侧表面，连续进入侧表面的第一开口和位于侧表面上的第二开口; 引导部分，设置在第二开口处; 从导入部延伸到处理槽中并具有端子部的管路; 以及设置在管道处的多个排出孔。多个排出孔包括第一排出孔和第二排出孔，第二排出孔相对于第一排出孔靠近端子部侧。每个第一排出孔的开口面积大于每个第二排出孔的开口面积。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2007042736A Semiconductor device and electronic module, and process for manufacturing electronic module 审中-公开
标题翻译：半导体器件和电子模块，以及制造电子模块的过程
公开(公告)号：JP2007042736A
公开(公告)日：2007-02-15
申请号：JP2005222747
申请日：2005-08-01
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： ASAKAWA TATSUHIKO
IPC分类号： H01L21/60
CPC分类号： H01L21/563 , H01L24/10 , H01L24/13 , H01L24/29 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05644 , H01L2224/13 , H01L2224/13099 , H01L2224/73203 , H01L2224/83192 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/0132 , H01L2924/07802 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2924/3511 , H01L2924/00 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of high packaging performance and a highly reliable electronic module, and to provide a process for manufacturing an electronic module. SOLUTION: The semiconductor device comprises a semiconductor chip 10 having electrodes 14, a plurality of resin protrusions 20 formed on the surface of the semiconductor chip 10 where the electrodes 14 are formed, and interconnect lines 30 connected electrically with the electrodes 14 and formed on any resin protrusions. The resin protrusions 20 are formed to increase the height as they recede from the center of the surface of the semiconductor chip 10 where the electrodes 14 are formed. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有高封装性能和高可靠性电子模块的半导体器件，并提供一种用于制造电子模块的工艺。解决方案：半导体器件包括具有电极14的半导体芯片10，形成在形成有电极14的半导体芯片10的表面上的多个树脂突起20以及与电极14电连接的互连线30和在任何树脂突起上形成。形成树脂突起20，以便在从形成有电极14的半导体芯片10的表面的中心离开时增加高度。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2011114184A Etching method, and electronic device 审中-公开
标题翻译：蚀刻方法和电子设备
公开(公告)号：JP2011114184A
公开(公告)日：2011-06-09
申请号：JP2009269674
申请日：2009-11-27
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： ASAKAWA TATSUHIKO
IPC分类号： H01L21/306 , G02F1/1345 , H01L21/3213 , H03H3/08
摘要： PROBLEM TO BE SOLVED: To provide an etching method of uniformly etching the entire surface of a processed layer to be etched. SOLUTION: The etching method is designed to process an Au film (processed layer) 5 formed on a crystal substrate (substrate) 2 into a predetermined shape, wherein the Au film 5 is etched into a plurality of SAW patterns 3 as the predetermined shape, and during the etching, the crystal substrate 2 is arranged with the side of the Au film 5 down in a state wherein the crystal substrate 2 is dipped in an etchant 21. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供均匀蚀刻被蚀刻处理层的整个表面的蚀刻方法。解决方案：蚀刻方法被设计为将形成在晶体基板（基板）2上的Au膜（处理层）5处理成预定形状，其中将Au膜5蚀刻成多个SAW图案3，如并且在蚀刻期间，在晶体基板2浸渍在蚀刻剂21中的状态下，晶体基板2以Au膜5的一侧向下排列。（C）2011，JPO＆INPIT

6. 发明专利

JP2008205078A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008205078A
公开(公告)日：2008-09-04
申请号：JP2007037620
申请日：2007-02-19
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： ASAKAWA TATSUHIKO
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/52
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L2224/0236 , H01L2224/0401 , H01L2224/11515 , H01L2224/1191 , H01L2224/13008 , H01L2224/1319 , H01L2224/13562 , H01L2224/13582 , H01L2224/136 , H01L2224/1369 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/0665 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To improve reliability in wiring formed on a passivation film.
SOLUTION: A semiconductor substrate 10 is prepared, where it has the passivation film 16 that is formed at the upper portion of an integrated circuit 12 and has an irregular surface, and an electrode 14 that is connected to the integrated circuit 12 electrically and is exposed from the passivation film 16 at least partially. A resin layer 20 is formed on the passivation film 16. A second resin layer 22 is formed so that the passivation film 16 and the first resin layer 20 are covered. Wiring 30 is formed so that it passes an area on the second resin layer 22 at the upper portion of the passivation film 16 from an area on the electrode 14 and reaches an area on the second resin layer 22 at the upper portion of the first resin layer 20.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高钝化膜上形成的布线的可靠性。解决方案：制备半导体衬底10，其中其具有形成在集成电路12的上部并具有不规则表面的钝化膜16，以及与集成电路12电连接的电极14 并且至少部分地从钝化膜16暴露出来。树脂层20形成在钝化膜16上。第二树脂层22形成为钝化膜16和第一树脂层20被覆盖。形成布线30，使得其在钝化膜16的上部的第二树脂层22上的区域从电极14的区域通过，并到达第一树脂的上部的第二树脂层22上的区域第20层。（C）2008年，JPO＆INPIT

7. 发明专利

JP2010182991A Semiconductor device, and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010182991A
公开(公告)日：2010-08-19
申请号：JP2009027065
申请日：2009-02-09
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： ASAKAWA TATSUHIKO
IPC分类号： H01L21/3205 , H01L21/60 , H01L23/52
CPC分类号： H01L24/11 , H01L24/05 , H01L24/13 , H01L24/14 , H01L2224/02377 , H01L2224/02381 , H01L2224/0392 , H01L2224/0401 , H01L2224/05124 , H01L2224/11515 , H01L2224/1155 , H01L2224/1182 , H01L2224/11848 , H01L2224/13008 , H01L2224/13012 , H01L2224/1319 , H01L2224/13566 , H01L2224/13582 , H01L2224/13644 , H01L2224/13666 , H01L2224/1401 , H01L2224/14151 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/3025 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device high in connection reliability between an electrode and a wire; and a method of manufacturing the semiconductor device.
SOLUTION: The method of manufacturing the semiconductor device includes processes of: preparing a structure 1 including a semiconductor substrate 10, electrodes 14 formed on a first surface 11 of the semiconductor substrate 10, and an insulation film 16 formed on the first surface 11 and having openings 16a each located on a first part of the electrode 14; forming first metal layers 17 each extending from the surface of the first part of the electrode 14 to the surface of the insulation film 16; forming a resin layer 30 on first parts 19 of the first metal layers 17 located on the first parts of the electrodes 14 and on the insulation film 16 after the process of forming the first metal layers 17; forming resin projections 18 by removing at least second parts located on the first parts 19 of the first metal layers 17 of the resin layer 30 by leaving a first part of the resin layer 30; and forming second metal layers 20 electrically-connected to the electrodes 14 from the surfaces of the first metal layers 17 to the surfaces of the resin projections 18.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种电极和线之间的连接可靠性高的半导体器件; 以及半导体器件的制造方法。解决方案：制造半导体器件的方法包括以下处理：制备包括半导体衬底10的结构1，形成在半导体衬底10的第一表面11上的电极14和形成在第一表面上的绝缘膜16 并且具有各自位于电极14的第一部分上的开口16a; 形成从电极14的第一部分的表面延伸到绝缘膜16的表面的第一金属层17; 在形成第一金属层17的过程之后，在位于电极14的第一部分上的第一金属层17的第一部分19和绝缘膜16上形成树脂层30; 通过离开树脂层30的第一部分，去除位于树脂层30的第一金属层17的第一部分19上的至少第二部分来形成树脂突起18; 并且形成从第一金属层17的表面电连接到电极14到树脂突起18的表面的第二金属层20.版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2008205292A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008205292A
公开(公告)日：2008-09-04
申请号：JP2007041092
申请日：2007-02-21
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： ASAKAWA TATSUHIKO
IPC分类号： H01L21/3205 , H01L23/12 , H01L23/52
CPC分类号： H01L24/13 , H01L22/32 , H01L24/11 , H01L24/83 , H01L24/90 , H01L2224/02313 , H01L2224/0401 , H01L2224/13099 , H01L2224/1319 , H01L2224/16 , H01L2224/90 , H01L2924/0001 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/07811 , H01L2924/14 , H01L2924/3512 , H01L2924/00 , H01L2924/0665 , H01L2924/00014 , H01L2224/83851
摘要： PROBLEM TO BE SOLVED: To prevent cracks from occurring in a semiconductor substrate on which an integrated circuit is formed. SOLUTION: On the semiconductor substrate 10, the integrated circuit 12 is formed, and an electrode 14 is connected to the integrated circuit 12 electrically. A first resin layer 30 is formed in a first region 20 overlapping with the integrated circuit 12 on the surface of the semiconductor substrate 10, where the electrode 14 is formed. Wiring 40 is connected to the electrode 14 electrically and is formed on the first resin layer 30. In a second region 22 surrounding the first region 20 outside on the surface of the semiconductor substrate 10, a second resin layer 32 is formed apart from the first resin layer 30. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了防止在其上形成集成电路的半导体衬底中发生裂纹。解决方案：在半导体衬底10上形成集成电路12，电极14与集成电路12电连接。第一树脂层30形成在半导体衬底10的形成有电极14的表面上与集成电路12重叠的第一区域20中。配线40与电极14电连接并形成在第一树脂层30上。在半导体衬底10的表面外围包围第一区域20的第二区域22中，形成第二树脂层32，树脂层30.版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2008205077A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008205077A
公开(公告)日：2008-09-04
申请号：JP2007037619
申请日：2007-02-19
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： ASAKAWA TATSUHIKO
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/52
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To improve reliability in wiring formed on a passivation film. SOLUTION: A semiconductor substrate 10 is prepared, where it has the passivation film 16 that is formed at the upper portion of an integrated circuit 12 and has an irregular surface, and an electrode 14 that is connected to the integrated circuit 12 electrically and is exposed from the passivation film 16 at least partially. A resin layer 18 is formed on the passivation film 16. A resin section 24 is formed so that a recess 22 is buried while avoiding at least the upper end of a projection 20 on the irregular surface. Wiring 26 is formed so that it ranges from the electrode 14 to the resin layer 18. The wiring 26 is formed so that it adheres to the resin section 24 for burying the projection 20 and the recess 22 in the passivation film 16 between the electrode 14 and the resin layer 18. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高钝化膜上形成的布线的可靠性。解决方案：制备半导体衬底10，其中其具有形成在集成电路12的上部并具有不规则表面的钝化膜16，以及与集成电路12电连接的电极14 并且至少部分地从钝化膜16暴露出来。树脂层18形成在钝化膜16上。树脂部分24形成为使得凹陷22被埋入，同时至少避免凸起20在不规则表面上的上端。布线26形成为从电极14到树脂层18的范围。布线26形成为使其粘附到树脂部分24，以将突起20和凹部22埋在电极14之间的钝化膜16中和树脂层18.版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2007019104A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007019104A
公开(公告)日：2007-01-25
申请号：JP2005196644
申请日：2005-07-05
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： OBARA HIROSHI , HASHIMOTO NOBUAKI , ASAKAWA TATSUHIKO
IPC分类号： H01L21/3205 , H01L21/60 , H01L23/52
CPC分类号： H01L2224/0231 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/11 , H01L2224/13 , H01L2224/13099 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve the adhesiveness of a conductive layer and to prevent migration. SOLUTION: The manufacturing method of the semiconductor device comprises processes of: (a) forming a resin layer 20 above a semiconductor substrate 10 having an electrode pad 16 and a passivation film 18; (b) forming a resin projection 40 by curing the resin layer 20; (c) forming the conductive layer 50 which is electrically connected to the electrode pad 16 and passes over the resin projection 40. Before at least the process (b), a surface treatment is applied to at least a peripheral region 32 of the resin layer 20 to improve the wettability of the resin layer 20 with the resin material. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提高导电层的粘附性并防止迁移。解决方案：半导体器件的制造方法包括以下处理：（a）在具有电极焊盘16和钝化膜18的半导体衬底10上形成树脂层20; （b）通过固化树脂层20形成树脂突起40; （c）形成电连接到电极焊盘16并通过树脂突起40的导电层50.在至少工艺（b）之前，对树脂层的至少周边区域32施加表面处理以提高树脂层20与树脂材料的润湿性。版权所有（C）2007，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式