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1. 发明专利

JP2008034652A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008034652A
公开(公告)日：2008-02-14
申请号：JP2006206967
申请日：2006-07-28
申请人： Sanyo Electric Co Ltd , Sanyo Handotai Seizo Kk , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋半導体製造株式会社 , 三洋電機株式会社
发明人： MITA KEIJI , TAMADA YASUHIRO , OYA KENTARO
IPC分类号： H01L21/331 , H01L21/8224 , H01L21/8228 , H01L27/082 , H01L29/73 , H01L29/732
CPC分类号： H01L29/735 , H01L29/1008 , H01L29/167 , H01L29/6625
摘要： PROBLEM TO BE SOLVED: To solve the problem, wherein it is difficult in a conventional semiconductor device, for example, a lateral pnp transistor to obtain a desired current amplification factor, without making the device size to be large, while maintaining breakdown voltage characteristics. SOLUTION: The semiconductor device has an n-type epitaxial layer 4 formed on a p-type single-crystal silicon substrate 3. In the lateral pnp transistor 1, its epitaxial layer 4 is used as the base region. Then molybdenum (Mo) is diffused into the substrate 3 and epitaxial layer 4. According to this structure, desired current amplification factor (hFE) for the lateral pnp transistor 1 can be realized by adjusting the value of the base current. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题为了解决这样一个问题，即在常规的半导体器件例如横向pnp晶体管中难以获得期望的电流放大系数，而不会使器件尺寸变大，同时保持击穿电压特性。解决方案：半导体器件具有形成在p型单晶硅衬底3上的n型外延层4.在横向pnp晶体管1中，其外延层4用作基极区。然后，钼（Mo）扩散到衬底3和外延层4中。根据该结构，可以通过调节基极电流的值来实现横向pnp晶体管1的期望电流放大系数（hFE）。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2011077484A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011077484A
公开(公告)日：2011-04-14
申请号：JP2009230466
申请日：2009-10-02
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , Sanyo Semiconductor Manufacturing Co Ltd , 三洋半導体株式会社 , 三洋半導体製造株式会社 , 三洋電機株式会社
发明人： MITA KEIJI , TAMADA YASUHIRO , TAKAHASHI MASAO , MARUYAMA TAKAO
IPC分类号： H01L29/861 , H01L21/822 , H01L27/04
CPC分类号： H01L29/8611 , H01L27/0814
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where a full-wave rectifying circuit which is free of a leakage current generated by a parasitic transistor etc., and has high efficiency is constituted by forming a series diode group of diodes with high breakdown voltage and low on-resistance characteristics and forming a bridge of two series diode groups. SOLUTION: The semiconductor device has the series diode group formed by connecting a diode including a P type semiconductor substrate 1 as an anode and an N type buried layer 2 as a cathode, and a diode including a P+ type conductive layer 8 as an anode and an N type epitaxial layer 5 as a cathode to each other in series by an electrode AC1. In this case, an N+ type buried layer 3 and an N+ type conductive layer 7 are formed to prevent the N+ type buried layer 3 from having lower potential than that of the P+ type buried layer 4 even if a large positive voltage is applied to the electrode AC1, thereby preventing the parasitic transistor comprising the P+ type buried layer 4, the N+ type buried layer 3, and the P type semiconductor 1 as an emitter, a base, and a collector from being turned on. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体器件，其中不存在由寄生晶体管等产生的并且具有高效率的漏电流的全波整流电路通过形成串联二极管组的二极管构成，高击穿电压和低导通电阻特性，形成两个串联二极管组的桥。解决方案：半导体器件具有串联二极管组，其通过将包括作为阳极的P型半导体衬底1和作为阴极的N型掩埋层2的二极管和包括P +型导电层8的二极管作为阴极的阳极和N型外延层5通过电极AC1串联。在这种情况下，形成N +型掩埋层3和N +型导电层7，以防止N +型埋层3的电位低于P +型掩埋层4的电位，即使施加大的正电压电极AC1，从而防止包括P +型掩埋层4，N +型掩埋层3和作为发射极，基极和集电极的P型半导体1的寄生晶体导通。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2011077483A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011077483A
公开(公告)日：2011-04-14
申请号：JP2009230465
申请日：2009-10-02
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , Sanyo Semiconductor Manufacturing Co Ltd , 三洋半導体株式会社 , 三洋半導体製造株式会社 , 三洋電機株式会社
发明人： MITA KEIJI , TAMADA YASUHIRO , TAKAHASHI MASAO , MARUYAMA TAKAO
IPC分类号： H01L29/78 , H01L21/331 , H01L21/76 , H01L21/761 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L29/732 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where a high breakdown voltage IGBT which does not generate a leakage current by a parasitic NPN transistor is formed basically through a bipolar high breakdown voltage vertical PNP process. SOLUTION: The semiconductor device has, on a P type semiconductor substrate 1, a P+ type collector layer 8 electrically connected to a collector electrode 15 of an IGBT, a P+ type buried layer 4 connected with the P+ type collector layer 8, an N type buried layer 2 below the P+ type buried layer 4, and an N+ type buried layer 3 between the P+ type buried layer 4 and the N type buried layer 2. Furthermore, an N+ type conductive layer 7 is formed which is united with an end of the N+ type buried layer 3, extends to a surface of an N type epitaxial layer 5 formed on the P type semiconductor substrate 1, and is electrically connected to the collector electrode 15. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其中基本上通过双极高击穿电压垂直PNP工艺形成不产生由寄生NPN晶体管产生漏电流的高击穿电压IGBT。解决方案：半导体器件在P型半导体衬底1上具有电连接到IGBT的集电极15的P +型集电极层8，与P +型集电极层8连接的P +型掩埋层4， P +型掩埋层4以下的N型掩埋层2和P +型掩埋层4与N型埋层2之间的N +型掩埋层3.此外，形成N +型导电层7，其与 N +型掩埋层3的端部延伸到形成在P型半导体基板1上的N型外延层5的表面，并与集电极15电连接。（C）2011， JPO＆INPIT

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