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1. 发明专利

JP2010238994A Semiconductor module and method of manufacturing the same 审中-公开
标题翻译：半导体模块及其制造方法
公开(公告)号：JP2010238994A
公开(公告)日：2010-10-21
申请号：JP2009086619
申请日：2009-03-31
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NAKAZATO MAYUMI , INOUE YASUNORI , MIZUHARA HIDEKI , USUI RYOSUKE
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/07802 , H01L2924/1461 , H01L2924/15787 , H01L2924/19105 , H01L2924/3025 , H01L2224/85 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor module which can be packaged in three dimensions, and to provide a method of manufacturing the same. SOLUTION: A semiconductor element 11 on a substrate 10 is covered with a first insulating resin 14, and the conductive pattern 15 of a package is connected to a second conductive pattern 21B through a buried electrode 25 provided in the contact hole 24 of the first insulating resin 14. Further, the conductive pattern 15 of the package is covered with a second insulating resin 27, and has a first external electrode 28 at its opening. Namely, the semiconductor module which can be packaged in three dimensions is obtained by forming the external electrode on a surface. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以三维封装的半导体模块，并提供一种制造该半导体模块的方法。解决方案：衬底10上的半导体元件11被第一绝缘树脂14覆盖，并且封装的导电图案15通过设置在接触孔24中的埋入电极25连接到第二导电图案21B 第一绝缘树脂14.此外，封装的导电图案15被第二绝缘树脂27覆盖，并且在其开口处具有第一外部电极28。也就是说，可以通过在表面上形成外部电极来获得三维可封装的半导体模块。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2009290141A Semiconductor module and method for manufacturing the same, and mobile device 审中-公开
标题翻译：半导体模块及其制造方法以及移动设备
公开(公告)号：JP2009290141A
公开(公告)日：2009-12-10
申请号：JP2008143787
申请日：2008-05-30
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： USUI RYOSUKE , INOUE YASUNORI , MIZUHARA HIDEKI , NAKAZATO MAYUMI
IPC分类号： H01L23/00
CPC分类号： H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor module having a simple configuration in which electromagnetic interference is suppressed. SOLUTION: The method for manufacturing a semiconductor module includes the steps of: preparing a semiconductor module 10 having a semiconductor element 14 mounted on a substrate for mounting an element; placing a metal foil 30 on the top surface of a package 28 including the semiconductor element 14; and reforming the shape of a part of the metal foil 30 that is not covering the top surface of the package 28 so as to follow the side faces of the package 28. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有抑制电磁干扰的简单结构的半导体模块。解决方案：制造半导体模块的方法包括以下步骤：制备半导体模块10，其具有安装在用于安装元件的基板上的半导体元件14; 将金属箔30放置在包括半导体元件14的封装28的顶表面上; 并且改变未覆盖包装28的顶面的金属箔30的一部分的形状，以便跟随包装28的侧面。（C）2010年，JPO和INPIT

3. 发明专利

JP2009110891A Mobile equipment 审中-公开
标题翻译：移动设备
公开(公告)号：JP2009110891A
公开(公告)日：2009-05-21
申请号：JP2007284595
申请日：2007-10-31
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KOMURA TETSUJI , HIGASHIYAMA NOBUYUKI , MIZUHARA HIDEKI
IPC分类号： H01H13/14 , G06F3/02 , H01H13/702 , H04M1/23
摘要： PROBLEM TO BE SOLVED: To suppress a local temperature rise of a key part in a mobile equipment at which a plurality of keys are installed.
SOLUTION: A PDA as the mobile equipment includes a substrate 20, an exothermic semiconductor element 30 installed at a first main surface S1 of the substrate 20, a plurality of switches 22 installed at a second main surface S2 of the substrate 20, a key mat 40 positioned on the second main surface S2 side of the substrate 20, a plurality of protruding parts 24 protruded toward one main surface of the key mat 40 opposing to the second main surface S2 of the substrate 20 from the plurality of respective switches 22, and a key 16 which is installed at the other main surface of the key mat 40, and which can be depressed against the key mat 40. A contact face of the protruding part 24a protruding from a specified switch 22a of which the distance from the semiconductor element 30 in a surface direction of the substrate 20 is within a prescribed range and a key mat 40 has a smaller area compared with the contact face of the protruding part 24b protruded from an unspecified switch 22b except the specified switch 22a with the key mat 40.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：抑制安装有多个键的移动设备中的关键部件的局部温度上升。解决方案：作为移动设备的PDA包括基板20，安装在基板20的第一主表面S1处的放热半导体元件30，安装在基板20的第二主表面S2处的多个开关22，定位在基板20的第二主表面S2侧的键垫40，多个突出部24，从多个相应的开关朝向与基板20的第二主表面S2相对的键垫40的一个主表面突出 22，以及安装在键垫40的另一个主表面上并且能够抵靠键垫40的键16。突起部分24a的接触面从指定开关22a突出，基板20的表面方向上的半导体元件30处于规定范围内，并且与从未指定的开关22b突出的突出部24b的接触面相比，键垫40的面积小使用键垫40指定开关22a。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008294415A Element packaging board and method for manufacturing same, semiconductor module and method for manufacturing same, and portable device 审中-公开
标题翻译：元件包装板及其制造方法，半导体模块及其制造方法和便携式设备
公开(公告)号：JP2008294415A
公开(公告)日：2008-12-04
申请号：JP2008099483
申请日：2008-04-07
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NAKAZATO MAYUMI , MIZUHARA HIDEKI
IPC分类号： H01L23/12 , H01L21/3205 , H01L23/52 , H05K3/46
CPC分类号： H01L2224/05548 , H01L2224/13022
摘要： PROBLEM TO BE SOLVED: To provide a technology for forming wiring without causing much damage to a circuit element. SOLUTION: The method for manufacturing a semiconductor module includes: a first process of forming a conductive bump 20 on one surface of an insulating layer 16; a second process of exposing the conductive bump 20 from the other surface of the insulating layer 16; a third process of providing a first wiring layer 18 on an exposed area of the conductive bump 20 and on the other surface of the insulating layer 16; a fourth process of preparing a semiconductor substrate on which a circuit element is formed, an electrode being formed on a surface of the substrate; and a fifth process of embedding the conductive bump 20 in the insulating layer 16 by press-bonding the insulating layer 16 and the semiconductor substrate in a state where the conductive bump 20 on which the first wiring layer 18 is provided by the third process is disposed counter to the electrode. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于形成布线的技术，而不会对电路元件造成很大的损害。解决方案：制造半导体模块的方法包括：在绝缘层16的一个表面上形成导电凸块20的第一工艺; 将导电凸块20从绝缘层16的另一表面露出的第二工序; 在导电凸块20的暴露区域和绝缘层16的另一个表面上提供第一布线层18的第三工序; 制备其上形成有电路元件的半导体衬底的第四工艺，在衬底的表面上形成电极; 以及在通过第三处理设置有第一布线层18的导电凸块20的状态下，通过将绝缘层16和半导体基板压接而将导电凸块20嵌入绝缘层16中的第五工序对着电极。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008172213A Semiconductor module, method for manufacturing the same and mobile apparatus 审中-公开
标题翻译：半导体模块，其制造方法和移动设备
公开(公告)号：JP2008172213A
公开(公告)日：2008-07-24
申请号：JP2007314241
申请日：2007-12-05
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NAKAZATO MAYUMI , SHIBATA SEIJI , OKAYAMA YOSHIHISA , USUI RYOSUKE , MIZUHARA HIDEKI
IPC分类号： H01L23/12
CPC分类号： H01L2924/014
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing technology capable of improving the reliability of a semiconductor module having a via contact connected to an electrode part of a semiconductor device.
SOLUTION: A conductive bump 5a is formed on an insulating layer 4 and arranged so that the tip part of the conductive bump 5a is in contact with the surface of an electrode 2 of a semiconductor substrate 1. By pressure-molding the arranged assembly by using a press machine, the semiconductor substrate 1, the conductive bump 5a and the insulating layer 4 are integrated. Thereby, the conductive bump 5a is allowed to embed itself in the insulating layer 4 while maintaining contact with the electrode 2. The insulating layer 4 is subjected to laser irradiation from above so as to form an aperture part 7 exposing the conductive bump 5a. Then, the upper surface of the insulating layer 4 and the inner surface of the aperture part 7 are plated with copper by an electroless plating method and an electroplating method to form a copper plating layer 8 on the insulating layer 4 and a via contact 8b is formed in the aperture part 7 so as to coat the inwall of the aperture part 7.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够提高具有连接到半导体器件的电极部分的通孔接触的半导体模块的可靠性的制造技术。解决方案：导电凸块5a形成在绝缘层4上，并且布置成使得导电凸块5a的顶端部分与半导体衬底1的电极2的表面接触。通过压力成形布置通过使用压机，半导体基板1，导电凸块5a和绝缘层4的组装是一体的。由此，能够将导电性凸块5a自身嵌入绝缘层4，同时保持与电极2的接触。绝缘层4从上方受到激光照射，形成露出导电凸块5a的开口部7。然后，绝缘层4的上表面和开口部7的内表面通过化学镀法和电镀法镀铜，以在绝缘层4上形成镀铜层8，并且通孔接触8b为形成在孔部7中，以便覆盖开口部分7的内壁。版权所有：（C）2008，JPO＆INPIT

6. 发明专利

JP2007067238A Flexible substrate 审中-公开
标题翻译：柔性基板
公开(公告)号：JP2007067238A
公开(公告)日：2007-03-15
申请号：JP2005252623
申请日：2005-08-31
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： OKUDA MICHINORI , YAMASHITA TOMIO , NAKAZATO MAYUMI , MIZUHARA HIDEKI , USUI RYOSUKE
IPC分类号： H05K1/03
摘要： PROBLEM TO BE SOLVED: To inhibit a flexible substrate from coming off a connector or misalignment from being produced between the flexible substrate and the connector when the former is connected to the latter provided on a circuit device. SOLUTION: A flexible substrate 10 has a support film 20, wiring layers 30 and 31, and resin layers 40 and 41, wherein fillers 50 and 51, whose average grain diameter is larger than the thickness of the resin layers 40 and 41, are imbedded in the resin layers 40 and 41. The fillers 50 and 51 are made of a material having a degree of hardness higher than the resin for the connector to which the flexible substrate 10 is connected. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：当前者连接到设置在电路装置上的柔性基板和连接器时，阻止柔性基板从柔性基板和连接器之间产生的连接器脱落或不对准。解决方案：柔性基板10具有支撑膜20，布线层30和31以及树脂层40和41，其中平均粒径大于树脂层40和41的厚度的填料50和51 填充在树脂层40和41中。填料50和51由硬度高于连接柔性基板10所连接的树脂的硬度的材料制成。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2007067237A Circuit substrate, circuit arrangement, and flexible board 审中-公开
标题翻译：电路基板，电路布置和灵活板
公开(公告)号：JP2007067237A
公开(公告)日：2007-03-15
申请号：JP2005252622
申请日：2005-08-31
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： YAMASHITA TOMIO , NAKAZATO MAYUMI , OKUDA MICHINORI , USUI RYOSUKE , MIZUHARA HIDEKI , TAKAKUSAKI SADAMICHI
IPC分类号： H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a circuit substrate and circuit arrangement that can improve thermal conductivity of the circuit substrate and can easily and surely control a fill amount of a filler. SOLUTION: A circuit substrate 10 has a wiring layer 20 composed of a copper foil, and an insulating substrate 30 formed on the wiring layer 20. The insulating substrate 30 includes an insulating resin film 32 and a filler 34. A plurality of holes 33 are formed in the insulating resin film 32 in its thickness direction such that they are arranged in an orderly manner. The plurality of holes 33 go right through the insulating resin film 32. The holes 33 are filled with the filler 34 that has a thermal conductivity higher than that of the insulating resin film 32 and is insulating. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供可以提高电路基板的导热性的电路基板和电路装置，并且可以容易且可靠地控制填充物的填充量。解决方案：电路基板10具有由铜箔构成的布线层20和形成在布线层20上的绝缘基板30.绝缘基板30包括绝缘树脂膜32和填充物34。在绝缘树脂膜32的厚度方向上形成孔33，使得它们以有序的方式排列。多个孔33直接通过绝缘树脂膜32.孔33填充有导热率高于绝缘树脂膜32的填充物34，并且绝缘。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2007012829A Circuit device 审中-公开
标题翻译：电路设备
公开(公告)号：JP2007012829A
公开(公告)日：2007-01-18
申请号：JP2005190852
申请日：2005-06-30
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： USUI RYOSUKE , MIZUHARA HIDEKI , INOUE YASUNORI
IPC分类号： H01L25/04 , H01L25/18
CPC分类号： H01L24/82 , H01L2224/24 , H01L2224/24145 , H01L2224/24195 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve reliability of a circuit device wherein a plurality of circuit elements are mounted on a substrate made of metal or semiconductor.
SOLUTION: A plurality of circuit elements 142a (an element that does not operate stably under a predetermined low temperature range) and 142b (an element provided with a resistance heating body 142b1 as a heat generating source) are embedded in an insulating resin film 122 and a circuit element such as a passive element 144 or the like, and are provided on a substrate 140 formed of a three-layer structure clad material. A heat from the heat generating source included in the circuit element 142b is conducted to the substrate 140, so as to heat the circuit element 142a.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提高其中多个电路元件安装在由金属或半导体制成的基板上的电路装置的可靠性。解决方案：将多个电路元件142a（在预定的低温范围内不稳定的元件）和142b（设置有作为发热源的电阻加热体142b1的元件）嵌入绝缘树脂薄膜122和诸如无源元件144等的电路元件，并且设置在由三层结构复合材料形成的基板140上。来自包括在电路元件142b中的发热源的热量被传导到基板140，以便加热电路元件142a。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006332564A Method for manufacturing circuit device 有权
标题翻译：制造电路装置的方法
公开(公告)号：JP2006332564A
公开(公告)日：2006-12-07
申请号：JP2005158070
申请日：2005-05-30
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： USUI RYOSUKE , MIZUHARA HIDEKI , INOUE YASUNORI
IPC分类号： H01L23/12 , G01C19/5783 , H01L25/00 , H01L25/04 , H01L25/18
CPC分类号： H01L2224/48091 , H01L2224/73265 , H01L2924/1815 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a circuit device which contributes to downsizing and improvement of connection reliability.
SOLUTION: The method for manufacturing a circuit device is provided with processes of: forming first isolation grooves 36A from the surface of conductive foil 30 so that a first conductive pattern 13 and a second conductive pattern 14 may be protruded, and forming a second isolation groove 36B from the surface of the conductive foil 30 in its part to be bent; electrically connecting a first device 11 for detecting a physical quantity with the first conductive pattern 13, and connecting a second device 12 with the second conductive pattern 14; bending the conductive foil 30 at the point where the second isolation groove 36B is formed; forming a sealing resin 15 in such a way that it covers the two devices and fills the first isolation grooves 36A and the second isolation groove 36B; and removing the conductive foil 30 from its underside until the sealing resin 15 is exposed as filling the first isolation grooves 36A and the second isolation groove 36B.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种有助于小型化和提高连接可靠性的电路装置的制造方法。解决方案：制造电路器件的方法具有以下工艺：从导电箔30的表面形成第一隔离槽36A，使得可以突出第一导电图案13和第二导电图案14，并形成第二隔离槽36B从导电箔30的表面弯曲成一部分; 将用于检测物理量的第一装置11与第一导电图案13电连接，以及将第二装置12与第二导电图案14连接; 在形成第二隔离槽36B的位置弯曲导电箔30; 形成密封树脂15，使其覆盖两个装置并填充第一隔离槽36A和第二隔离槽36B; 并且从其下侧除去导电箔30，直到填充第一隔离槽36A和第二隔离槽36B而露出密封树脂15为止。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2005109067A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005109067A
公开(公告)日：2005-04-21
申请号：JP2003339123
申请日：2003-09-30
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： USUI RYOSUKE , MIZUHARA HIDEKI , NAKAMURA TAKESHI
IPC分类号： H01L23/12 , H01L21/68 , H01L23/31 , H01L23/498 , H01L25/16 , H05K3/24 , H05K3/30 , H05K3/34 , H05K3/38
CPC分类号： H01L21/6835 , H01L23/3128 , H01L23/498 , H01L24/45 , H01L24/48 , H01L25/16 , H01L2221/68345 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/13055 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H05K3/244 , H05K3/305 , H05K3/3452 , H05K3/381 , H05K2201/0989 , H05K2203/049 , H05K2203/095 , Y10S438/906 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To suppress defective connections between a semiconductor chip and a wiring layer in a semiconductor package, and to improve reliability and yield in an element. SOLUTION: An adhesive film 464 is formed on the surface of an electrode film 462, and a covering film 466 is formed on the adhesive film. As the component materials of the adhesive film 464 nickel, chrome, molybdenum, tungsten, aluminum, the alloy of them, and the like are used. As the component materials of the covering film 466, gold, silver, platinum, the alloy of them, and the like are used. COPYRIGHT: (C)2005,JPO&NCIPI

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