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1. 发明专利

JP2013132174A Charge/discharge controller 有权
标题翻译：充电/放电控制器
公开(公告)号：JP2013132174A
公开(公告)日：2013-07-04
申请号：JP2011281520
申请日：2011-12-22
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KOSONE MAKOTO
IPC分类号： H02J3/32 , G06Q50/06 , H01M10/44 , H02J3/46 , H02J7/00 , H02J7/35
CPC分类号： Y02P90/50
摘要： PROBLEM TO BE SOLVED: To perform charge/discharge control economically.SOLUTION: The charge/discharge controller controls exchange of power between a power generator, a battery, a load, and a power system via a power conversion unit. A charge/discharge control unit sets a charging fee (fee required for charging) when utilizing commercial AC power, by adding an extra charge (power conversion loss in terms of charge) to the power charge of each time zone, and also sets the charging fee when utilizing the generated power by using the extra charge. When charging is performed actually, the values of a plurality of charging capacities are held, while dividing the whole charging capacity of the battery into a plurality of charging capacities (CC, CC) corresponding to a plurality of charging fees (CST, CST). Thereafter, when there is a charging capacity (CC) corresponding to a charging fee lower than the current power charge (13 yen/kWh), discharge of the battery is permitted within a limit of that charging capacity.
摘要翻译：要解决的问题：经济地进行充放电控制。解决方案：充放电控制器通过电源转换单元控制发电机，电池，负载和电力系统之间的电力交换。充电/放电控制单元通过在每个时区的电力充电中加入额外的费用（充电的电力转换损失）来设定利用商用交流电的充电费（充电所需的费用），还设定充电通过使用额外的费用来利用所产生的电力时的费用。当实际进行充电时，保持多个充电容量的值，同时将电池的整个充电容量分成与多个充电费（CST，CST）相对应的多个充电容量（CC，CC）。此后，当存在对应于低于当前电力充电（13日元/ kWh）的充电费用的充电容量（CC）时，在该充电容量的限制内允许电池的放电。

2. 发明专利

JP2010097356A Arithmetic processor, communication equipment and broadcasting receiver mounted with the same, and information processor 审中-公开
标题翻译：算术处理器，通信设备和与之相连的广播接收器和信息处理器
公开(公告)号：JP2010097356A
公开(公告)日：2010-04-30
申请号：JP2008266788
申请日：2008-10-15
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KOSONE MAKOTO
IPC分类号： G06F7/00
摘要： PROBLEM TO BE SOLVED: To improve processing performance of an arithmetic part while handling address generation of arithmetic data where an address to be accessed depends on an arithmetic result. SOLUTION: A control part 20 supplies setting data to an arithmetic part 10 for changing a function. A storage part 30 stores arithmetic data to be processed by the arithmetic part 10. An address is supplied from the control part 20 to a first storage area in the storage part 30. An address is supplied from the arithmetic part 10 to a second storage region in the storage part 30. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提高运算部分的处理性能，同时处理要访问的地址取决于算术结果的算术数据的地址生成。解决方案：控制部分20将设置数据提供给用于改变功能的算术部分10。存储部30存储由运算部10处理的算术数据。从控制部20向存储部30的第一存储区域提供地址。从运算部10向第二存储区域在存储部分30中。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2007316901A Control information supply device and control information compression method 有权
标题翻译：控制信息提供装置和控制信息压缩方法
公开(公告)号：JP2007316901A
公开(公告)日：2007-12-06
申请号：JP2006145166
申请日：2006-05-25
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： HIRAMATSU TATSUO , KOSONE MAKOTO , IIZUKA KAZUHISA
IPC分类号： G06F15/80 , G06F9/38
摘要： PROBLEM TO BE SOLVED: To reduce the memory region of a command RAM for command storage to be supplied to an ALU relating to parallel processing.
SOLUTION: An NOP(XX) and a specific command DU are removed from an original command sequence 61 showing a command sequence to be originally supplied to four ALUs operating in parallel to generate a compression command sequence 62. In this case, an index 63 showing a removed part is also generated. At a circuit side which actually supplies the command, the compression command sequence 62 and the index 63 are referred to. When the index 63 shows that the NOP(XX) or the specific command DU has been removed from the compression command sequence 62, a specific command DU is supplied to the ALU, and in the other case, the command included in the compression command sequence 62 is supplied.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：减少要提供给与并行处理有关的ALU的命令存储的命令RAM的存储区域。解决方案：从原始命令序列61中删除NOP（XX）和特定命令DU，该原始命令序列61示出最初提供给并行操作的四个ALU的命令序列，以生成压缩命令序列62.在这种情况下，也产生了表示被去除部分的索引63。在实际提供命令的电路侧，参考压缩命令序列62和索引63。当索引63示出NOP（XX）或特定命令DU已经从压缩命令序列62中移除时，特定命令DU被提供给ALU，在另一种情况下，包括在压缩命令序列中的命令 62。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007172400A Processor 有权
标题翻译：处理器
公开(公告)号：JP2007172400A
公开(公告)日：2007-07-05
申请号：JP2005370914
申请日：2005-12-22
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KOSONE MAKOTO , OKADA MAKOTO
IPC分类号： G06F15/80 , G06F7/00 , H03K19/173
摘要： PROBLEM TO BE SOLVED: To provide a processor provided with a reconfigurable circuit contributing to reduction in a circuit scale. SOLUTION: This processor including the reconfigurable circuit 1 provided with a computing part constituted of a plurality of logic circuits capable of executing selectively a plurality of arithmetic logic computation functions respectively, and a connection part for holding a connection relation between the plurality of logic circuits, is provided with a memory 5 for storing a data used in the logic circuit, a division storage means for dividing the data into a plurality of portions having the bit number of memory words, to be stored in the plurality of memory words, when the bit number of the data stored in the memory 5 exceeds the bit number of memory words assigned by one address of the memory 5, and a continuous reading means for restoring the data stored in the plurality of memory words divided by the division storage means, to the original bit number of data, when read from the plurality of memory words. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有有助于减小电路规模的可重构电路的处理器。解决方案：该处理器包括可重配置电路1，该可重配置电路1设置有由能够选择性地执行多个算术逻辑计算功能的多个逻辑电路构成的计算部分，以及用于保持多个逻辑电路设置有用于存储在逻辑电路中使用的数据的存储器5，用于将数据分割成具有存储在多个存储字中的位数的多个部分的分割存储装置，当存储器5中存储的数据的位数超过由存储器5的一个地址分配的存储器字的位数时，以及连续读取装置，用于恢复由分割存储装置划分的多个存储字中存储的数据当从多个存储器字读取数据时，到原始位数。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006040254A Reconfigurable circuit and processor 有权
标题翻译：可重构电路和处理器
公开(公告)号：JP2006040254A
公开(公告)日：2006-02-09
申请号：JP2005130462
申请日：2005-04-27
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NAKAJIMA HIROSHI , KOSONE MAKOTO , IIZUKA KAZUHISA
IPC分类号： G06F7/00 , G06F12/06 , G06F15/80 , H03K19/173 , H03K19/177
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit device having a reconfigurable circuit in which change of a function is possible. SOLUTION: The integrated circuit device 26 is provided with the reconfigurable circuit 12 on which a plurality of threads are simultaneously executed. A RAM provided to a memory part 27 is assigned to the threads to be executed on the reconfigurable circuit 12. A first switching part in a first switching circuit 23 is provided for every RAM, selects output from the reconfigurable circuit 12 according to the threads and supplies it to the RAM. When transfer of data is performed between the threads, assignment of the thread to the RAM is changed after completion of all the thread processing. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有能够改变功能的可重构电路的集成电路装置。解决方案：集成电路装置26设置有可同时执行多个线程的可重构电路12。将提供给存储器部分27的RAM分配给要在可重新配置电路12上执行的线程。为每个RAM提供第一切换电路23中的第一切换部分，根据线程从可重新配置电路12中选择输出，提供给RAM。当在线程之间执行数据传输时，在完成所有线程处理之后，更改线程到RAM的分配。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2013138540A Power conversion device 有权
标题翻译：电源转换器件
公开(公告)号：JP2013138540A
公开(公告)日：2013-07-11
申请号：JP2011287472
申请日：2011-12-28
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KOSONE MAKOTO
IPC分类号： H02J3/46 , H02J3/32 , H02J7/35
摘要： PROBLEM TO BE SOLVED: To suppress frequent switching between power input/output that may be caused during constant power charging or the like.SOLUTION: A power conversion circuit 20 transmits and receives power among a power storage device 3, a power generation device 4 and a power system 5. In constant charge control, a control section 23 charges the power storage device 3 with constant electric power, using a power generated by the power generation device 4. If the generated power is insufficient, an insufficient amount of power is input from the power system 5 to the power conversion circuit 20, and if the generated power is surplus, a surplus amount of power is output from the power conversion circuit 20 to the power system 5. When the generated power of the power generation device 4 is almost equal to the constant electric power, power input/output is repeatedly switched between the power conversion circuit 20 and the power system 5. If such switching is detected or predicted, a power point of the power generation device 4 is changed from the maximum power point of an MPPT control to suppress the switching.
摘要翻译：要解决的问题：抑制在恒功率充电等期间可能引起的电力输入/输出之间的频繁切换。电力转换电路20在蓄电装置3，发电装置4和发电装置4之间发送和接收电力电力系统5.在恒定充电控制中，控制部分23使用由发电装置4产生的电力以恒定电力对蓄电装置3充电。如果发电量不足，则输入的功率不足从电力系统5到电力转换电路20，如果发电功率过剩，则从功率转换电路20向电力系统5输出剩余电力。当发电装置4的发电量为几乎等于恒定电力，电力输入/输出在功率转换电路20和电力系统5之间重复切换。如果检测或预测这种切换，则ap 发电装置4的点从MPPT控制的最大功率点变化，抑制切换。

7. 发明专利

JP2013138538A Power conversion device 有权
标题翻译：电源转换器件
公开(公告)号：JP2013138538A
公开(公告)日：2013-07-11
申请号：JP2011287461
申请日：2011-12-28
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NORISADA TAKAAKI , ITO KAZUO , KOSONE MAKOTO
IPC分类号： H02J7/35 , H02J3/32
摘要： PROBLEM TO BE SOLVED: To suppress frequent switching between power input/output that may be caused during constant power charging or the like.SOLUTION: A power conversion circuit 20 transmits and receives power among a power storage device 3, a power generation device 4 and a power system 5. In constant charge control, a control section 23 charges the power storage device 3 with constant electric power, using a power generated by the power generation device 4. If the generated power is insufficient, an insufficient amount of power is input from the power system 5 to the power conversion circuit 20, and if the generated power is surplus, a surplus amount of power is output from the power conversion circuit 20 to the power system 5. When the generated power of the power generation device 4 is almost equal to the constant electric power, power input/output is repeatedly switched between the power conversion circuit 20 and the power system 5. If such switching is detected or predicted, a charge command power is changed from the constant electric power to suppress the switching.
摘要翻译：要解决的问题：抑制在恒功率充电等期间可能引起的电力输入/输出之间的频繁切换。电力转换电路20在蓄电装置3，发电装置4和发电装置4之间发送和接收电力电力系统5.在恒定充电控制中，控制部分23使用由发电装置4产生的电力以恒定电力对蓄电装置3充电。如果发电量不足，则输入的功率不足从电力系统5到电力转换电路20，如果发电功率过剩，则从功率转换电路20向电力系统5输出剩余电力。当发电装置4的发电量为几乎等于恒定电力，功率输入/输出在功率转换电路20和电力系统5之间重复切换。如果检测或预测这种切换，则ac harge命令功率从恒定电力变化以抑制切换。

8. 发明专利

JP2007272394A Date flow graph reconfiguration device, setting data generation device of reconfigurable circuit, processor, and reconfigurable circuit 有权
标题翻译：日期流图重构装置，可重构电路，处理器和可重新配置电路的数据生成装置的设置
公开(公告)号：JP2007272394A
公开(公告)日：2007-10-18
申请号：JP2006095161
申请日：2006-03-30
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： OKADA MAKOTO , IIZUKA KAZUHISA , KOSONE MAKOTO
IPC分类号： G06F17/50 , G06F7/00
CPC分类号： Y02D10/12
摘要： PROBLEM TO BE SOLVED: To further miniaturize a data flow graph required for setting operations of a reconfigurable circuit more than the conventional technique so as to achieve the reduced power consumption of the reconfigurable circuit. SOLUTION: A data flow graph processing unit 31 optimizes a data flow graph generated from a compile unit 30 into a data flow graph capable of being mapped in the most suitable form for a reconfigurable circuit 12. The processing unit 31 deletes continuous through nodes which performs only data propagation from upper stage nodes to lower stage nodes, and converts the data flow graph so as to propagate the data to be propagated from the upper stage nodes to the lower stage nodes through an inside state circuit 20. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了进一步小型化可重构电路的操作所需的数据流图，比传统技术更为小型化，以便实现可重构电路的降低的功耗。解决方案：数据流图处理单元31将从编译单元30生成的数据流图优化为能够以最适合的形式映射到可重构电路12的数据流图。处理单元31删除连续通过仅执行从上级节点到下级节点的数据传播的节点，并且转换数据流图，以便通过内部状态电路20传播要从上级节点传播到下级节点的数据。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007241694A Arithmetic mapping method to reconfigurable circuit, reconfigurable circuit and data flow graph 有权
标题翻译：可重构电路，可重构电路和数据流图的算术映射方法
公开(公告)号：JP2007241694A
公开(公告)日：2007-09-20
申请号：JP2006063741
申请日：2006-03-09
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： OKADA MAKOTO , KOSONE MAKOTO
IPC分类号： G06F7/00 , H03K19/173
摘要： PROBLEM TO BE SOLVED: To provide an arithmetic mapping method to a reconfigurable circuit for reducing a circuit scale, and for shortening processing time and the reconfigurable circuit using the arithmetic mapping method. SOLUTION: This arithmetic mapping method for mapping an expected operation function to a reconfigurable circuit equipped with an arithmetic part configured of a plurality of logic circuits capable of selectively executing a plurality of arithmetic logical operation functions and a connection part for holding a connection relation between the plurality of logic circuits comprises a number of valid bit decision step for deciding the number of valid bits input to the input of the expected operation function and a mapping step for mapping the expected operation function to the reconfigurable circuit based on the number of valid bits decided in the valid bit number decision step. Also, this arithmetic mapping method comprises a code decision step for deciding the code of the input of the expected operation function and a mapping step for mapping the expected operation function to the reconfigurable circuit based on the code decided by the code decision step. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了减少电路规模的可重构电路以及使用算术映射方法缩短处理时间和可重构电路，提供算术映射方法。解决方案：用于将期望的操作功能映射到配备有能够选择性地执行多个算术逻辑运算功能的多个逻辑电路配置的运算部的可重构电路的算术映射方法和用于保持连接的连接部多个逻辑电路之间的关系包括用于确定输入到期望操作功能的输入的有效位的数目的数量的有效位决定步骤和用于将预期操作功能映射到可重新配置电路的映射步骤，在有效位数决定步骤中决定有效位。此外，该算术映射方法包括：代码判定步骤，用于决定预期操作功能的输入代码;以及映射步骤，用于基于由代码判定步骤决定的代码将预期操作功能映射到可重构电路。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2006065787A Data flow graph processing method and reconfigurable circuit 有权
标题翻译：数据流图形处理方法和可重构电路
公开(公告)号：JP2006065787A
公开(公告)日：2006-03-09
申请号：JP2004250670
申请日：2004-08-30
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： OKADA MAKOTO , KOSONE MAKOTO
IPC分类号： G06F17/50 , H03K19/173
摘要： PROBLEM TO BE SOLVED: To provide a technique for processing a data flow graph necessary for setting operation of a reconfigurable circuit. SOLUTION: The data flow graph processing method expresses as a node a function of a logic circuit included in the reconfigurable circuit and generates a DFG including a node accessible to a memory (S12). A write node accessible to the memory is expressed as mem_w, whereas a read node is expressed as mem_r. Indices are added to these memory access nodes (S16). The indices show order by which the memory is accessed in the DFG. Thus, a DGF including the memory access nodes is created. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于处理设置可重新配置电路的操作所需的数据流程图的技术。解决方案：数据流图处理方法将可重构电路中包括的逻辑电路的功能表示为节点，并生成包括存储器可访问的节点的DFG（S12）。存储器可访问的写入节点表示为mem_w，而读取节点表示为mem_r。指标被添加到这些存储器访问节点（S16）。这些指标显示了在DFG中访问存储器的顺序。因此，创建包括存储器访问节点的DGF。版权所有（C）2006，JPO＆NCIPI

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