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JP2011216092A Simulation device and method for reconfigurable processor 有权
标题翻译：用于可重构加工器的模拟装置和方法
公开(公告)号：JP2011216092A
公开(公告)日：2011-10-27
申请号：JP2011076608
申请日：2011-03-30
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： OH TAE-WOOK , RYU SOO JUNG , KIM YOON-JIN , SEO WOONG , CHO YOUNG-CHUL , PARK IL-HYUN
IPC分类号： G06F9/455 , G06F11/00 , G06F11/25 , H01L21/82
CPC分类号： G06F17/5054 , G06F17/5022 , G06F17/5077
摘要： PROBLEM TO BE SOLVED: To provide a processor simulation technique used for evaluating the performance of a processor executing an application or for forming an application executable in the processor in an optimum manner.SOLUTION: The simulation device for a reconfigurable processor including some function units models the processor by expressing a routing path between a function unit generating an operand and a function unit consuming the operand by a queue. The size of such a queue is determined based on information on a delay of routing between function units and stage information of an iteration loop by modulo scheduling received from a schedular. The device includes a modeling code DB storing host binary codes related to the operation of each routing queue, and executes a corresponding host binary code as substitute for a binary file to perform a simulation.
摘要翻译：要解决的问题：提供一种用于评估执行应用的处理器的性能或者以最佳方式在处理器中形成可执行应用的处理器的处理器模拟技术。解决方案：用于可重构处理器的模拟设备，包括一些功能单元模型所述处理器通过在产生操作数的功能单元和通过队列消耗所述操作数的功能单元之间表达路由路径。基于从模块接收到的模调度，基于功能单元之间的路由延迟和迭代循环的阶段信息的信息来确定这样的队列的大小。该设备包括存储与每个路由队列的操作相关的主机二进制代码的建模代码DB，并且执行相应的主机二进制代码以代替二进制文件来执行仿真。

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