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1. 发明专利

JP2007250621A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007250621A
公开(公告)日：2007-09-27
申请号：JP2006068853
申请日：2006-03-14
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHIBA KAZUYOSHI , TANIGUCHI YASUHIRO , OWADA FUKUO , YAMAKOSHI HIDEAKI
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8247 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce manufacturing cost of a MIS transistor having three kinds of gate insulated film thickness on the principal surface of the same semiconductor substrate.
SOLUTION: A p-type well PW is formed with common use of an n-channel low voltage resistance MIS in a low voltage resistance MIS region, and a well of an n-channel low voltage resistance MIS in an intermediate voltage resistance MIS region. In the same way, an n-type well NW is formed with common use of a p-channel low voltage resistance MIS and a well of a p-channel low voltage resistance MIS. Moreover, an n-type extension region 9 is formed with common use of an n-channel intermediate voltage resistance MIS of an intermediate voltage resistance MIS region and an extension region of an n-channel high voltage resistance MIS in a high voltage resistance MIS region. In the same way, a p-type extension region 10 is formed with common use of a p-channel intermediate voltage resistance MIS, and an extension region of a p-channel high voltage resistance MIS in a high voltage resistance MIS region.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了降低在同一半导体衬底的主表面上具有三种栅极绝缘膜厚度的MIS晶体管的制造成本。解决方案：在低电压电阻MIS区域中通常使用n沟道低电压电阻MIS的p型阱PW，以及在中压电阻中的n沟道低电压电阻MIS的阱 MIS区域。以同样的方式，通常使用p沟道低电压电阻MIS和p沟道低电压电阻MIS的阱来形成n型阱NW。另外，在高电压电阻MIS区域中，通常使用中压电阻MIS区域的n沟道中压电阻MIS和n沟道高电压电阻MIS的延伸区域，形成n型延伸区域9 。以同样的方式，通常使用p沟道中压电阻MIS和在高电压电阻MIS区域中的p沟道高电压电阻MIS的延伸区域形成p型延伸区域10。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2006040985A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006040985A
公开(公告)日：2006-02-09
申请号：JP2004215061
申请日：2004-07-23
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KANAMARU TAKAHIRO , YAMAKOSHI HIDEAKI , SAITO KENTARO , KAWASHIMA YOSHIYUKI , NISHIBE SENICHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce the chances of disturbance faults occurring in a memory cell having a MONOS structure.
SOLUTION: A semiconductor device has a structure such that a memory gate having the MONOS structure is formed on the principal plane of a semiconductor substrate, and a sidewall is formed on the side face of the memory gate. In forming the sidewall on the side face of the memory gate, a bottom silicon oxide film having the MONOS structure is removed from the lower part of the sidewall, and thereafter, the sidewall is formed on the side face of the memory gate.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：减少在具有MONOS结构的存储单元中发生的干扰故障的机会。解决方案：半导体器件具有这样的结构，使得具有MONOS结构的存储栅极形成在半导体衬底的主平面上，并且侧壁形成在存储栅极的侧面上。在形成存储器栅极侧面的侧壁时，从侧壁的下部去除具有MONOS结构的底部氧化硅膜，之后在存储栅极的侧面上形成侧壁。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2007227585A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007227585A
公开(公告)日：2007-09-06
申请号：JP2006046228
申请日：2006-02-23
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TANIGUCHI YASUHIRO , SHIBA KAZUYOSHI , OWADA FUKUO , YAMAKOSHI HIDEAKI
IPC分类号： H01L27/10 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of accelerating a size reduction of a semiconductor device where memory cells and a peripheral circuit are formed on the same semiconductor substrate, and improving the characteristics of MISFETs that are used in the memory cells and the peripheral circuit at the same time. SOLUTION: A p-type semiconductor region 45 is formed as a pocket region below a channel forming region 25 in a memory cell forming region. In the p-type semiconductor region 45, the position of an impurity concentration peak is located separate from the forming position of a low-concentration n-type impurity diffusion region 44. That is, the p-type semiconductor region 45 formed in the memory cell forming region is provided at a deeper position than the p-type semiconductor region 48 formed in a low-dielectric strength MISFET forming region. Furthermore, the impurity concentration of the low-concentration n-type impurity diffusion region 44 formed in the memory cell forming region is set lower than that of a low-concentration n-type impurity diffusion region 50 formed in a high-dielectric strength MISFET forming region. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供能够加速在同一半导体衬底上形成存储单元和外围电路的半导体器件的尺寸减小的技术，并且提高在存储单元中使用的MISFET的特性和外围电路同时进行。解决方案：在存储单元形成区域中的沟道形成区域25的下方形成p型半导体区域45作为口袋区域。在p型半导体区域45中，杂质浓度峰的位置与低浓度n型杂质扩散区域44的形成位置分离。也就是说，形成在存储器中的p型半导体区域45 电池形成区域设置在比形成在低介电强度MISFET形成区域中的p型半导体区域48的深的位置处。此外，形成在存储单元形成区域中的低浓度n型杂质扩散区域44的杂质浓度设定为低于在高介电强度MISFET形成中形成的低浓度n型杂质扩散区域50的杂质浓度地区。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007165361A Semiconductor integrated circuit device and its manufacturing method 审中-公开
标题翻译：半导体集成电路设备及其制造方法
公开(公告)号：JP2007165361A
公开(公告)日：2007-06-28
申请号：JP2005355883
申请日：2005-12-09
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： TANIGUCHI YASUHIRO , SHIBA KAZUYOSHI , OWADA FUKUO , YAMAKOSHI HIDEAKI
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To make the dual gate of a semiconductor integrated circuit device wherein a high withstand voltage complementary MISFET and a low withstand voltage complementary MISFET are formed on the same semiconductor substrate.
SOLUTION: An energy for implanting P ions to adjust a threshold voltage of a high withstand voltage p-channel MISFET is made larger than an energy for implanting B ions to adjust a threshold voltage of a high withstand voltage n-channel MISFET. In addition, when the B ions are implanted into an undoped silicon film in a p-channel MISFET formation area so as to convert it into a p-type silicon film 9p, the concentration of B of the p-type silicon film 9p adjacent to the boundary with a gate insulating film 8 is controlled to 2×10
20 atoms/cm
3 or less.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在同一半导体衬底上形成高耐压互补MISFET和低耐压互补MISFET的半导体集成电路器件的双栅极。解决方案：用于植入P离子以调节高耐压p沟道MISFET的阈值电压的能量大于用于注入B离子以调整高耐压N沟道MISFET的阈值电压的能量。此外，当在P沟道MISFET形成区域中将B离子注入未掺杂的硅膜中以将其转换为p型硅膜9p时，p型硅膜9p的B的浓度相邻与栅极绝缘膜8的边界被控制为2×10 30原子/ cm 3 / SP 3或更小。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2010093154A Nonvolatile semiconductor memory device and method for manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2010093154A
公开(公告)日：2010-04-22
申请号：JP2008263541
申请日：2008-10-10
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMABE KAZUHARU , TANIGUCHI YASUHIRO , YOSHIDA SEIJI , OWADA FUKUO , OKA YASUSHI , YAMAKOSHI HIDEAKI , HOSODA NAOHIRO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device for being further miniaturized by realizing downsizing and high-densification of memory cells constituting the nonvolatile semiconductor memory device. SOLUTION: A source line SL is formed between a memory cell MC1 and a memory cell MC2, in the manner of self-alignment. Concretely, the source line SL is formed so as to contact with both sidewalls SWs formed on a sidewall of a memory gate electrode MG1 and on a sidewall of a memory gate electrode MG2, in the manner of self-alignment. Further, not only the memory gate electrodes MG1, MG2 and MG, but also control gate electrodes CG1, CG2 and CG are formed in a sidewall shape. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过实现构成非易失性半导体存储器件的存储单元的小型化和高密度化，提供一种进一步小型化的非易失性半导体存储器件。解决方案：以自对准的方式在存储单元MC1和存储单元MC2之间形成源极线SL。具体地说，源极线SL形成为以自对准的方式与形成在存储栅极电极MG1的侧壁上的两个侧壁SW和存储栅极电极MG2的侧壁接触。此外，不仅存储栅极电极MG1，MG2和MG，而且控制栅极电极CG1，CG2和CG都形成为侧壁形状。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2007208152A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007208152A
公开(公告)日：2007-08-16
申请号：JP2006027828
申请日：2006-02-06
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMAKOSHI HIDEAKI , SHIBA KAZUYOSHI , TANIGUCHI YASUHIRO , OWADA FUKUO
IPC分类号： H01L27/08 , H01L21/265 , H01L21/76 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide techniques for lowering the cost of a semiconductor device and techniques for forming a well matching characteristics of a memory cell and a high-dielectric-strength MISFET. SOLUTION: A resist pattern 25 is formed which covers memory cell formation regions M1 to M3 and a low-dielectric-strength MISFET formation region T, and exposes a high-dielectric-strength MISFET formation region K. This resist pattern 25 is used as a mask to form a p-type well 26 in the high-dielectric-strength MISFET formation region K. Then a channel formation region 27 is formed by using the resist pattern 25 as a mask. Further, a resist pattern is formed which covers the high-dielectric-strength MISFET formation region K and low-dielectric-strength MISFET formation region T and exposes the memory cell formation regions M1 to M3. This resist pattern is used as a mask to form a p-type well and a channel formation region in the memory cell formation regions M1 to M3. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供用于降低半导体器件的成本的技术和用于形成存储器单元和高介电强度MISFET的良好匹配特性的技术。解决方案：形成覆盖存储单元形成区域M1至M3和低介电强度MISFET形成区域T并且暴露高介电强度MISFET形成区域K的抗蚀剂图案25.该抗蚀剂图案25是用作掩模以在高介电强度MISFET形成区域K中形成p型阱26.然后通过使用抗蚀剂图案25作为掩模形成沟道形成区域27。此外，形成覆盖高介电强度MISFET形成区域K和低介电强度MISFET形成区域T并使存储单元形成区域M1至M3露出的抗蚀剂图案。该抗蚀剂图案用作掩模以在存储单元形成区域M1至M3中形成p型阱和沟道形成区域。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006173199A Method of manufacturing semiconductor apparatus 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006173199A
公开(公告)日：2006-06-29
申请号：JP2004360303
申请日：2004-12-13
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMAKOSHI HIDEAKI , SHIBA KAZUYOSHI
IPC分类号： H01L27/11 , H01L21/8244 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To provide technology for improving reliability of a semiconductor apparatus having SRAM.
SOLUTION: An end of element separation 2 is covered with a second side wall 9a1 formed on the side wall of the pull-out GM2 of a gate electrode common to load MIS and driving MIS, which constitute a CMOS inverter. Thus, removal of a silicon oxide film constituting element separation 2 when a wiring groove HM1 is formed which is brought into contact with a drain (p
+ -type semiconductor region 13) of load MIS (Ld1) and the pull-out GM2 is suppressed to be smaller than depth of the p
+ -type semiconductor region 13 of load MIS (Ld1).
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供用于提高具有SRAM的半导体装置的可靠性的技术。解决方案：构成CMOS反相器的负载MIS和驱动MIS共同的栅电极的拉出GM2的侧壁上形成的第二侧壁9a1覆盖元件间隔2的端部。因此，当形成与负载MIS（Ld1）的漏极（p + 型半导体区域13）接触的布线槽HM1时去除构成元件间隔2的氧化硅膜，并且拉出GM2被抑制为小于负载MIS（Ld1）的p + 型半导体区域13的深度。版权所有（C）2006，JPO＆NCIPI

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