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1. 发明专利

JP2010147501A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010147501A
公开(公告)日：2010-07-01
申请号：JP2010047363
申请日：2010-03-04
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SATO YUKIHIRO , UNO TOMOAKI , MATSUURA NOBUYOSHI , SHIRAISHI MASAKI
IPC分类号： H01L25/04 , H01L25/18 , H02M3/155
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To make a non-insulated DC-DC converter compact and to improve the voltage conversion efficiency of the converter.
SOLUTION: In the non-insulated DC-DC converter having a circuit wherein a power MOSFET for a high-side switch and a power MOSFET for a low-side switch are connected in series, the power transistor for the high-side switch and the power transistor for the low-side transistor and a driver circuit which drives them are composed of semiconductor chips 5a, 5b and 5c different from each other; and the three semiconductor chips 5a, 5b, and 5c are stored in one package 6a, and the semiconductor chip 5a including the power transistor for the high-side switch and the semiconductor chip 5c including the driver circuit are arranged closely to each other.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：使非绝缘DC-DC转换器紧凑并提高转换器的电压转换效率。解决方案：在具有用于高侧开关的功率MOSFET和低侧开关的功率MOSFET串联连接的电路的非绝缘DC-DC转换器中，高边的功率晶体管开关和用于低端晶体管的功率晶体管和驱动它们的驱动电路由彼此不同的半导体芯片5a，5b和5c组成; 并且三个半导体芯片5a，5b和5c被存储在一个封装6a中，并且包括用于高侧开关的功率晶体管和包括驱动器电路的半导体芯片5c的半导体芯片5a彼此紧密地布置。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2008060256A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008060256A
公开(公告)日：2008-03-13
申请号：JP2006234061
申请日：2006-08-30
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KOIKE SHINYA , FUJISHIRO ATSUSHI , KIDO NORIO , SATO YUKIHIRO , NAKAMURA HIROYUKI
IPC分类号： H01L25/04 , H01L23/48 , H01L25/18
CPC分类号： H01L21/565 , H01L23/49503 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/34 , H01L24/36 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/91 , H01L2224/04042 , H01L2224/29111 , H01L2224/29139 , H01L2224/32245 , H01L2224/32257 , H01L2224/40095 , H01L2224/40245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48463 , H01L2224/4847 , H01L2224/49171 , H01L2224/49175 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/37099 , H01L2224/84801
摘要： PROBLEM TO BE SOLVED: To lay out the mounting wiring efficiently at mounting by changing the constitution of a semiconductor device. SOLUTION: A first and second chips 21, 22 are mounted on a first and second die pads 31, 32, respectively. The first and second die pads 31, 32 are divided and constituted in parallel to a first and second sides 41, 42 of a seal 40. This results in that an output pin 51 from the first chip 21 and a control pin 52 of a driving circuit may project in the opposite directions, and the wiring layout at mounting may be set to a minimum route. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过改变半导体器件的结构，在安装时有效地布置安装布线。解决方案：第一和第二芯片21,22分别安装在第一和第二芯片焊盘31,32上。第一和第二管芯焊盘31,32被分隔并且与密封件40的第一和第二侧面41,42平行地构成。这导致来自第一芯片21的输出引脚51和驱动的第一芯片21的控制引脚52 电路可能沿相反方向投影，并且安装时的布线布局可能设置为最小路线。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2005294871A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005294871A
公开(公告)日：2005-10-20
申请号：JP2005195940
申请日：2005-07-05
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SATO YUKIHIRO , DANNO TADATOSHI , IMAI TAKASHI
IPC分类号： H01L23/50
CPC分类号： H01L24/73 , H01L2224/05554 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a packaging technique by which a package having good high-frequency characteristics can be formed by reducing grounding inductance. SOLUTION: In a semiconductor device, a semiconductor chip mounted on the semiconductor chip mounting area of a tab, and leads which are arranged around the tab and become external terminals when the leads are exposed to the outside of a sealed body, are electrically connected to each other. The bonding area of the tab and the pad for power source circuit of a semiconductor chip are electrically connected to each other and the exposed portion of the tab is used as the external terminal for power source of the semiconductor device by exposing the portion to the outside of the sealed body. Since the exposed portion of the tab is used as the external terminal for grounding power source, the transmission route is shortened and the cross-sectional area of the route is increased as compared with the conventional semiconductor device using leads as external terminals. Consequently, the inductance and impedance of the semiconductor device can be reduced. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种通过降低接地电感可以形成具有良好高频特性的封装的封装技术。解决方案：在半导体器件中，安装在突片的半导体芯片安装区域上的半导体芯片，以及当引线暴露于密封体的外部时，布置在突片周围并成为外部端子的引线是彼此电连接。半导体芯片的突片和电源电路用焊盘的接合区域彼此电连接，并且通过将该部分暴露于外部，将突片的暴露部分用作半导体器件的电源的外部端子的密封体。由于突片的暴露部分被用作接地电源的外部端子，所以与使用引线作为外部端子的常规半导体器件相比，传输路径被缩短并且路径的横截面面积增加。因此，可以减小半导体器件的电感和阻抗。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005159238A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005159238A
公开(公告)日：2005-06-16
申请号：JP2003399196
申请日：2003-11-28
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SATO YUKIHIRO , NAMITA TOSHIYUKI , SHIMIZU KAZUO
IPC分类号： H01L23/28 , H01L23/29 , H01L23/48
CPC分类号： H01L24/97 , H01L2224/16245 , H01L2224/73253 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a small semiconductor device of a surface mounting structure wherein an electrode plate is exposed to an upper surface of a sealing member. SOLUTION: The semiconductor device comprises a sealing member having upper, lower and side surfaces; a semiconductor chip positioned in the sealing member and having source and gate electrodes on its first main surface and having a drain electrode on its second main surface; a drain electrode plate having the drain electrode of the semiconductor chip connected to its one surface and having the other surface exposed to the upper surface of the sealing member; source and gate electrode plates of a terminal structure, part of which is positioned in the interior of the sealing member to be connected to the gate and source electrodes of the semiconductor chip respectively and another part of which is projected from the side surface of the sealing member to be surface mounted on the second surface side of the sealing member; and a wiring terminal projected from one edge of the drain electrode plate and extended and bent along the side surface of the sealing member to be surface mounted on the lower surface side of the sealing member. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种表面安装结构的小型半导体器件，其中电极板暴露于密封构件的上表面。解决方案：半导体器件包括具有上表面，下表面和侧表面的密封构件; 半导体芯片，其位于所述密封构件中，并且在其第一主表面上具有源电极和栅电极，并且在其第二主表面上具有漏电极; 漏极电极板，其半导体芯片的漏极电极与其一个表面连接，另一个表面暴露于密封构件的上表面; 源极和栅极电极板，其一部分位于密封构件的内部，分别连接到半导体芯片的栅极和源极，另一部分从密封件的侧表面突出构件被表面安装在密封构件的第二表面侧上; 以及从漏极电极板的一个边缘突出并沿着密封构件的侧表面延伸并弯曲以将表面安装在密封构件的下表面侧上的接线端子。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2010123686A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010123686A
公开(公告)日：2010-06-03
申请号：JP2008294816
申请日：2008-11-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SATO YUKIHIRO , FUNATSU KATSUHIKO , NAKAMURA HIROYUKI
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L23/4334 , H01L23/49524 , H01L23/49562 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/91 , H01L2224/0603 , H01L2224/29111 , H01L2224/2919 , H01L2224/32245 , H01L2224/37011 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4847 , H01L2224/48599 , H01L2224/73215 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2224/85013 , H01L2224/92247 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0134 , H01L2924/014 , H01L2924/0665 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/30107 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a means for improving reliability of a semiconductor device. SOLUTION: A semiconductor chip 3 is mounted over a chip mounting portion 2 of a lead frame 41 via solder 11a. A metal plate 6 is arranged over a source pad electrode 3s of the semiconductor chip 3 and a lead portion 4a of a lead frame 41 via solder 11b, 11c. A solder reflow process is performed thereby to bond the semiconductor chip 3 over the chip mounting portion 2 with the solder 11a, and to bond the metal plate 6 to the source pad electrode 3a and the lead portion 4 with the solder 11b, 11c. The lead frame 41 is formed of a copper alloy, and thus has its softening temperature higher than the temperature of the solder reflow process. The metal plate 6 is formed of oxygen-free copper, and has its softening temperature lower than the temperature of the solder reflow process, whereby the metal plate 6 is softened in the solder reflow process. Thereafter, a gate pad electrode 3g of the semiconductor chip 3 is coupled to a lead portion 5a via a wire 7, a sealing resin portion 8 is formed, and then the lead frame 41 is cut. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于提高半导体器件的可靠性的手段。解决方案：半导体芯片3通过焊料11a安装在引线框架41的芯片安装部分2上。金属板6通过焊料11b，11c配置在半导体芯片3的源极焊盘电极3s和引线框41的引线部分4a的上方。进行焊锡回流处理，由此将焊料11a与半导体芯片3接合在芯片安装部2上，用焊料11b，11c将金属板6与焊盘电极3a和引线部4接合。引线框架41由铜合金形成，因此其软化温度高于焊料回流工艺的温度。金属板6由无氧铜形成，并且其软化温度低于回流焊接工艺的温度，由此金属板6在回流焊接过程中软化。此后，半导体芯片3的栅极焊盘电极3g通过导线7与引线部分5a连接，形成密封树脂部分8，然后切断引线框架41。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2008160163A Semiconductor device and method for manufacturing it, and electronic device 有权
标题翻译：半导体器件及其制造方法及电子器件
公开(公告)号：JP2008160163A
公开(公告)日：2008-07-10
申请号：JP2008075930
申请日：2008-03-24
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SATO YUKIHIRO , OTANI TAKESHI , TAKAHASHI HIROYUKI , NAMITA TOSHIYUKI , SHIMIZU KAZUO
IPC分类号： H01L23/34 , H01L21/60 , H01L23/48 , H01L25/07 , H01L25/18
CPC分类号： H01L24/73 , H01L2224/16245 , H01L2224/32245 , H01L2224/34 , H01L2224/45144 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/37099 , H01L2224/37599
摘要： PROBLEM TO BE SOLVED: To provide a new semiconductor device having a high heat radiation and superior in a connection reliability in packaging. SOLUTION: The semiconductor device has a semiconductor chip, a resin sealing body for sealing the semiconductor chip, a first conductive member connected to a first electrode on the first main surface of the semiconductor chip, and a second conductive member connected to the second electrode of a second main surface, being the opposite side to the first main surface of the semiconductor chip. The first conductive member exposes from the first main surface of the resin sealer, and the second conductive member is exposed from the second main surface and side surface opposite side to the first main surface of the resin sealing body. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有高散热性并且在包装中的连接可靠性优异的新半导体器件。解决方案：半导体器件具有半导体芯片，用于密封半导体芯片的树脂密封体，连接到半导体芯片的第一主表面上的第一电极的第一导电构件和连接到半导体芯片的第二导电构件第二主表面的第二电极，与半导体芯片的第一主表面相对。第一导电构件从树脂密封剂的第一主表面暴露，并且第二导电构件从与树脂密封体的第一主表面相反的第二主表面和侧表面露出。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2005026294A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005026294A
公开(公告)日：2005-01-27
申请号：JP2003187377
申请日：2003-06-30
申请人： Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ
发明人： SATO YUKIHIRO , NAMITA TOSHIYUKI
IPC分类号： H01L23/48 , H01L23/495
CPC分类号： H01L24/49 , H01L23/3107 , H01L23/3142 , H01L23/4952 , H01L23/49524 , H01L23/49562 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/97 , H01L29/7827 , H01L2224/02166 , H01L2224/04034 , H01L2224/04042 , H01L2224/05124 , H01L2224/05155 , H01L2224/05553 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/0603 , H01L2224/37124 , H01L2224/40091 , H01L2224/40245 , H01L2224/40247 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48472 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/4912 , H01L2224/49171 , H01L2224/49175 , H01L2224/49431 , H01L2224/73221 , H01L2224/8385 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/1811 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2924/2075
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which is low in ON-state resistance, capable of fixing a larger semiconductor chip on a support board, and has high electrical reliability. SOLUTION: The semiconductor device 1 is equipped with a metal header, a semiconductor chip forming a power MOSFET fixed on the metal header, a sealing body of insulating resin covering the semiconductor chip and the metal header, a drain lead 4 which is connected to the header and protrudes from the one side of the sealing body, a source lead 5 and a gate lead 6 protruding in parallel from the one side of the sealing body, and wires which are located inside the sealing body to connect electrodes on the top surface of the semiconductor chip to the source lead 5 and the gate lead 6. Furthermore, in the semiconductor device 1, a gate electrode pad is located close to the lead posts of the gate lead and the source lead, and a source electrode pad 11 is located distant from the lead posts. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造导通状态电阻低的半导体器件的方法，其能够将更大的半导体芯片固定在支撑板上，并且具有高的电可靠性。解决方案：半导体器件1配备有金属集管，形成固定在金属集管上的功率MOSFET的半导体芯片，覆盖半导体芯片和金属集管的绝缘树脂的密封体，排出引线4，连接到集管并从密封体的一侧突出，源极引线5和从密封体的一侧平行突出的栅极引线6以及位于密封体内部的电线，以连接电极半导体芯片的顶表面到源极引线5和栅极引线6.此外，在半导体器件1中，栅电极焊盘位于栅极引线和源极引线的引线柱附近，并且源电极焊盘 11位于远离引导柱的位置。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2004273977A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004273977A
公开(公告)日：2004-09-30
申请号：JP2003066205
申请日：2003-03-12
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KOIKE SHINYA , NAMITA TOSHIYUKI , NISHIKIZAWA ATSUSHI , SATO YUKIHIRO , SHIMIZU KAZUO
IPC分类号： H01L23/28 , H01L21/56 , H01L23/50
CPC分类号： H01L2224/16245 , H01L2224/32245 , H01L2224/73215 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, thin and small, and excellent in heat radiation. SOLUTION: The semiconductor device has a semiconductor chip having electrodes on its main and rear surfaces, a plurality of conductive leads comprising second parts and first parts which are thicker than the semiconductor chip, bump electrodes for connecting the second parts and semiconductor chip electrodes, and a sealant comprising a sealing resin that covers the semiconductor chip, the second parts of the leads, and the bump electrode region. The upper and lower surfaces of the first parts and one surface of each of the second parts are exposed out of the sealant, and the semiconductor chip rear surface is also exposed out of the sealant. The semiconductor device is rectangular in shape, and is uniform in thickness. The first parts are located along two sides facing each other, and semiconductor chip source/gate electrodes are connected to the second parts, which extend on the inner side of the first parts, via the bump electrodes. The gate electrode extends over a corner where two neighboring sides of the rectangle meet while the source electrode is arranged over the remaining four side sections. COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供薄且小且散热优异的半导体器件。解决方案：半导体器件具有在其主表面和后表面上具有电极的半导体芯片，多个导电引线，包括第二部分和比半导体芯片厚的第一部分，用于连接第二部分的凸起电极和半导体芯片电极和密封剂，其包括覆盖半导体芯片的密封树脂，引线的第二部分和凸起电极区域。第一部分的上下表面和每个第二部分的一个表面暴露在密封剂之外，并且半导体芯片后表面也暴露在密封剂之外。半导体器件的形状为矩形，厚度均匀。第一部分沿着彼此面对的两个侧面，并且半导体芯片源极/栅电极经由凸块电极连接到在第一部分的内侧延伸的第二部分。栅极电极在矩形的两个相邻边缘的角部延伸，而源电极布置在剩余的四个侧部上。版权所有（C）2004，JPO＆NCIPI

9. 发明专利

JP2004134605A Semiconductor device and its manufacturing process 审中-公开
公开(公告)号：JP2004134605A
公开(公告)日：2004-04-30
申请号：JP2002298308
申请日：2002-10-11
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SATO YUKIHIRO , NAGAMINE TORU
IPC分类号： H01L23/28 , H01L21/56
CPC分类号： H01L2224/05554 , H01L2224/32245 , H01L2224/48095 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To prevent hair cracks around the edge of a resin sealed body between terminals. SOLUTION: In a QFN-IC 25 comprising a resin sealed body 21 of a pellet 19, and a plurality of terminals 24 exposed at the circumferential edge part on the lower surface of the resin sealed body 21 where the pellet 19 and the terminals 24 are wire bonded in the resin sealed body 21, a beveled part 22 is formed at the circumferential edge part of the resin sealed body 21 between adjacent terminals 24 and 24. The beveled part 22 is molded simultaneously with the resin sealed body 21 by a protrusion 39 for forming a beveled part. The terminals 24 are cut at close proximity to the circumferential edge part of the resin sealed body 21. Since the beveled part is formed previously, generation of hair crack can be prevented at the circumferential edge part of the resin sealed body between the terminals when they are cut and thereby failure of mounting due to missing of the circumferential edge part starting from the hair crack can be avoided. COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2004134573A Semiconductor device and its manufacturing process 审中-公开
公开(公告)号：JP2004134573A
公开(公告)日：2004-04-30
申请号：JP2002297503
申请日：2002-10-10
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SATO YUKIHIRO , SHIMIZU KAZUO
IPC分类号： H01L23/12 , H01L21/56 , H01L23/50
CPC分类号： H01L2224/32245 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a process for manufacturing a leadless surface mount resin package IC. SOLUTION: After an adhesive tape 13 is bonded to the lower surface of a conductive substrate 11, the conductive substrate 11 is patterned to prepare a multi-terminal group frame 14 where a plurality of terminal groups 16, each having a chip mount part 17 and a plurality of terminals 18, are arranged in a frame 15. A chip 1 is bonded to the chip mount part 17 of each terminal group 16 and a wire 5 is bonded between the electrode pad 3 of the chip 1 and the terminal 18. The internal space of the frame 15 on the adhesive tape 13 is filled with sealing resin to mold a resin sealed body 21. The adhesive tape 13 is then stripped off from the resin sealed body 21 to expose the chip mount part 17 and the terminal 18. Subsequently, the resin sealed body 21 is cut into individual pieces. Since etching can be eliminated, the required man-hours can be reduced. Since the force to strip the adhesive tape is small, the terminal can be prevented from being stripped from the resin sealed body by the adhesive tape. COPYRIGHT: (C)2004,JPO

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