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1. 发明专利

JP2006215812A Dma controller 审中-公开
标题翻译： DMA控制器
公开(公告)号：JP2006215812A
公开(公告)日：2006-08-17
申请号：JP2005027878
申请日：2005-02-03
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MINEMATSU ISAO , KATAOKA TAKESHI , TANAKA SATOSHI
IPC分类号： G06F13/36 , G06F13/28
摘要： PROBLEM TO BE SOLVED: To provide a DMA controller usable with a small load on a CPU. SOLUTION: This DMA controller 20 performing data transfer between the CPU 11 connected to a CPU bus 1 and a timer 15 connected to an IO bus 2 operating at lower speed than the CPU bus 1 through a built-in RAM 10 connected to the CPU bus 1 has: a channel C0 inputted with transfer requirement of data from the preset timer 15 performing the transfer requirement of the data, having a transfer control part 24 transmitting a transfer instruction to the transfer requirement of the data; and a common control part 30 receiving the transfer instruction from the channel C0, and controlling the data transfer between the preset prescribed timer 15 and the built-in RAM 10 on the basis of the transfer instruction. The common control part 30 performs the data transfer once every time receiving the transfer instruction from the channel C0 when the transfer requirement is inputted to the channel C0. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可在CPU上使用小负载的DMA控制器。解决方案：该DMA控制器20通过连接到CPU总线1的内部RAM 10，在连接到CPU总线1的CPU 11和连接到IO总线2的定时器15之间执行数据传输，该IO总线2以比CPU总线1低的速度运行 CPU总线1具有：输入来自预设定时器15的数据的传送要求的信道C0，执行数据的传送要求，传输控制部分24将传输指令发送到数据的传送要求; 以及公共控制部分30，其从通道C0接收传送指令，并且基于传送指令控制预设的规定定时器15和内置RAM 10之间的数据传送。当传输要求被输入到信道C0时，公共控制部分30每次从信道C0接收到传送指令时执行数据传送一次。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2009048322A Interface module and semiconductor integrated circuit 审中-公开
标题翻译：接口模块和半导体集成电路
公开(公告)号：JP2009048322A
公开(公告)日：2009-03-05
申请号：JP2007212123
申请日：2007-08-16
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MINEMATSU ISAO
IPC分类号： G06F21/02 , G06F12/08 , G06F21/22
摘要： PROBLEM TO BE SOLVED: To disable a program stored in an NV memory and desired to be protected from being read by operand access, while enabling the program to be accessed at high speed by instruction fetches. SOLUTION: A BP monitor register 14 retains the BP bit information of each Flash module 20 after resetting is canceled and before it responds to access from a CPU core 30. A RAM transfer process unit 12 reads a program in a block to be protected within the Flash module 20 before responding to access from the CPU core 30, and transfers the program to a Protect-RAM 11 which is the same size as each block. A Flash IF 10 compares the address of an instruction fetch from the CPU core 30 with a value of the BP monitor register 14 and, if an access destination is the block to be protected, a selector process unit 13 selects a read from the Protect-Ram 11 and outputs the program of the read block to be protected to the CPU core 30. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：禁用存储在NV存储器中并希望被保护的程序不被操作数访问读取，同时使得能够通过指令读取高速访问程序。解决方案：在复位被取消之后并且在其响应来自CPU核心30的访问之前，BP监视器寄存器14保留每个闪存模块20的BP位信息.RAM传输处理单元12读取块中的程序在响应来自CPU核心30的访问之前在闪存模块20内保护，并将程序传送到与每个块大小相同的保护RAM 11。 Flash IF 10将来自CPU核心30的指令获取的地址与BP监视寄存器14的值进行比较，并且如果访问目的地是要保护的块，则选择器处理单元13选择从保护 - RAM 11，并将要保护的读块的程序输出到CPU内核30.版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2006302128A Information processor 有权
标题翻译：信息处理器
公开(公告)号：JP2006302128A
公开(公告)日：2006-11-02
申请号：JP2005125413
申请日：2005-04-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： INOUE HIDEO , MINEMATSU ISAO , IKENOBE TAKAHIRO
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： PROBLEM TO BE SOLVED: To provide an information processor allowing further securing of reliability of a received message of a CAN module by use of DMA transfer, and allowing high-speed data reading.
SOLUTION: The CAN module 25 receives the message from a CAN bus 15, and stores it in a message box unit of a message box 45. A reception requirement signal is outputted to a DMAC/IF 40 from the message box unit. The DMAC/IF 40 outputs a 7-bit requirement address together with a transfer requirement signal. A DMAC 30 accesses a memory 35 and the selected message box unit of the CAN module 25 on the basis of the 7-bit requirement address and the transfer requirement signal, and transfers the message stored in the selected message box unit to the memory 35.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种信息处理器，其允许通过使用DMA传输进一步确保CAN模块的接收消息的可靠性，并允许高速数据读取。解决方案：CAN模块25从CAN总线15接收消息，并将其存储在消息框45的消息框单元中。接收要求信号从消息盒单元输出到DMAC / IF 40。 DMAC / IF 40输出7位要求地址以及传输要求信号。 DMAC 30根据7位要求地址和传送要求信号访问存储器35和CAN模块25的所选择的消息盒单元，并将存储在所选消息盒单元中的消息传送到存储器35。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2004038642A Multiprocessor 审中-公开
公开(公告)号：JP2004038642A
公开(公告)日：2004-02-05
申请号：JP2002195836
申请日：2002-07-04
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MINEMATSU ISAO , SATO HISAKAZU
IPC分类号： G06F1/32 , G06F12/00 , G06F12/06 , G06F15/16 , G06F15/177
CPC分类号： Y02D10/13
摘要： PROBLEM TO BE SOLVED: To provide a power control method for a multiprocessor capable of reducing the waste of power consumption of a shared memory. SOLUTION: In this power control method for the multiprocessor, a memory device 7A (shared memory 71) shared by a CPU 3A and a coprocessor 5A has one or more banks 0-3, and the operation mode of each of banks 0-3 is independently switchable to any one of a plurality of operation modes differed in power consumption. In addition to the independently switching control of the operation mode of each of banks 0-3 of the shared memory 71 by the CPU 3A, the operation mode of each of banks 0-3 is independently switchably controlled also by the coprocessor 5A. COPYRIGHT: (C)2004,JPO

5. 发明专利

JP2004213540A Semiconductor storage device and software development system 审中-公开
标题翻译：半导体存储设备和软件开发系统
公开(公告)号：JP2004213540A
公开(公告)日：2004-07-29
申请号：JP2003002233
申请日：2003-01-08
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MINEMATSU ISAO , SATO HISAKAZU
IPC分类号： G06F12/08 , G06F9/38 , G06F9/45 , G06F12/00 , G06F13/28
CPC分类号： G06F9/3802 , G06F9/3814
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of guaranteeing an access cycle at the time of fetching an instruction and capable of improving the power efficiency of a processor system.
SOLUTION: An address range of an instruction string stored in an instruction buffer 13 is set in an address table 11. A judgment unit 12 judges whether an instruction address outputted from a CPU core is in the address range set in the address table 11 or not. A selector 14 selectively outputs an instruction code stored in an instruction buffer 13 and an instruction code stored in an instruction cache in accordance with the judged result of the judgment unit 12. In the case of fetching the instruction stored in the instruction buffer 13 by the CPU core, the access cycle is guaranteed and the operation of the instruction cache is not performed, so that the power efficiency can be improved.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：解决的问题：提供一种半导体存储装置，其能够保证在获取指令时的访问周期并且能够提高处理器系统的功率效率。解决方案：存储在指令缓冲器13中的指令串的地址范围被设置在地址表11中。判断单元12判断从CPU核心输出的指令地址是否在地址表中设置的地址范围内 11或不。选择器14根据判断单元12的判断结果选择性地输出存储在指令缓冲器13中的指令代码和存储在指令高速缓存中的指令代码。在将存储在指令缓冲器13中的指令取出的情况下， CPU核心，保证访问周期，不执行指令高速缓存的操作，从而提高电源效率。版权所有（C）2004，JPO＆NCIPI

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