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JP2014035753A Semiconductor device and electronic device 有权
标题翻译：半导体器件和电子器件
公开(公告)号：JP2014035753A
公开(公告)日：2014-02-24
申请号：JP2012178426
申请日：2012-08-10
申请人： Renesas Mobile Corp , ルネサスモバイル株式会社
发明人： SASAKI HAJIME , ITO HIROHIKO , NACHI SHIKIKO , NARUSE MINENOBU
IPC分类号： G06F1/10 , G01C21/26 , G06F1/12 , H03K5/135
CPC分类号： H03L7/08 , G06F1/10 , H03K5/135 , H03L7/18
摘要： PROBLEM TO BE SOLVED: To provide a high-quality semiconductor device suitable for an electronic device and the like.SOLUTION: A semiconductor device includes: a clock input circuit 14 that inputs an external clock signal; an input timing control PLL circuit 15 that adjusts the phases of the external clock signal and delay clock signal and generates an internal clock signal used for capturing input data; and a delay circuit 16 that delays the internal clock signal and outputs the delayed internal clock signal as the delay clock signal to an input timing control PLL circuit PLI. The semiconductor device also includes: an output timing control PLL circuit PLO that adjusts the phases of the external clock signal and delay clock signal and generates an internal clock signal used for outputting output data; and a delay circuit 18 that delays the internal clock signal and outputs the delayed internal clock signal as the delay clock signal to the output timing control PLL circuit PLO.
摘要翻译：要解决的问题：提供适合于电子设备等的高质量半导体器件。解决方案：半导体器件包括：输入外部时钟信号的时钟输入电路14; 输入定时控制PLL电路15，其调整外部时钟信号的相位和延迟时钟信号，并生成用于捕获输入数据的内部时钟信号; 以及延迟电路16，其延迟内部时钟信号并将延迟的内部时钟信号作为延迟时钟信号输出到输入定时控制PLL电路PLI。半导体器件还包括：输出定时控制PLL电路PLO，其调整外部时钟信号的相位和延迟时钟信号，并产生用于输出输出数据的内部时钟信号; 以及延迟电路18，其延迟内部时钟信号并将延迟的内部时钟信号作为延迟时钟信号输出到输出定时控制PLL电路PLO。

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