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1. 发明专利

JP2013020593A Semiconductor device, wireless communication terminal using the same, and power supply control method 审中-公开
标题翻译：半导体器件，使用相同的无线通信终端和电源控制方法
公开(公告)号：JP2013020593A
公开(公告)日：2013-01-31
申请号：JP2011155902
申请日：2011-07-14
申请人： Renesas Mobile Corp , ルネサスモバイル株式会社
发明人： ABE SHINYA , UCHIMURA YUTAKA , FUJIGAYA MASAKI
IPC分类号： G06F12/00 , G06F13/00 , G06F13/36 , G11C11/413
CPC分类号： Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： PROBLEM TO BE SOLVED: To solve the problem that a conventional semiconductor device has large power consumption.SOLUTION: In a semiconductor device 1 which includes: a storage area portion 16 for storing at least one of a program and data used by the program; a function block 11 for issuing an access request to the storage area portion 16 through a bus by execution of the program; and a bus state monitoring circuit 20 for monitoring a first signal REQ indicating the access request to the storage area portion 16 and a second signal GNT indicating an occupied state of a bus 23 by the storage area portion 16 that pass through the bus 23, controlling so that the storage area portion 16 is in a standby state in a time period during which access is not generated in the storage area portion 16, and controlling so that the storage area portion 16 is in an active state in a time period during which the access is generated in the storage area portion 16, the storage area portion 16 makes a voltage difference between a low potential side power supply voltage and a high potential side power supply voltage of a storage cell for storing the program or the data in the standby state smaller than that in the active state.
摘要翻译：解决的问题：为了解决传统的半导体器件具有大的功耗的问题。解决方案：在半导体器件1中，其包括：用于存储由程序使用的程序和数据中的至少一个的存储区域部分16; 功能块11，用于通过执行程序通过总线向存储区域部分16发出访问请求; 以及总线状态监视电路20，用于监视通过总线23的存储区域部分16指示对存储区域部分16的访问请求的第一信号REQ和指示总线23的占用状态的第二信号GNT，控制使得存储区域部分16在存储区域部分16中不产生访问的时间段内处于待机状态，并且在存储区域部分16中的存储区域部分16处于活动状态的时间段内处于活动状态在存储区域部分16中产生访问，存储区域部分16在用于存储程序的存储单元的低电位侧电源电压和高电位侧电源电压之间产生电压差，或者处于待机状态的数据小于活跃状态。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2014146095A Semiconductor device, electronic device, and method of controlling semiconductor device 有权
标题翻译：半导体器件，电子器件以及控制半导体器件的方法
公开(公告)号：JP2014146095A
公开(公告)日：2014-08-14
申请号：JP2013012958
申请日：2013-01-28
申请人： Renesas Mobile Corp , ルネサスモバイル株式会社
发明人： SADO TAKESHI , FUJIGAYA MASAKI , WAKAHARA KOHEI , HASEGAWA TAKASHI
IPC分类号： G06F1/32 , G06F1/04 , G06F15/78
CPC分类号： G06F1/324 , G06F1/3243 , Y02B60/1217 , Y02B60/1239 , Y02D10/126 , Y02D10/152
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of making performance respond to a dynamically varying load.SOLUTION: A semiconductor device includes CPU cores 1 to 4, frequency adjustment circuits FRC 1 to 4, and clock frequency control circuits CFCC 1 to 4. The frequency adjustment circuits FRC 1 to 4 include tables T1 to T4, T30, and T40. The frequency control circuits CFCC 1 to 4 supply clocks CK1 to CK4 to the CPU cores 1 to 4. The CPU cores 1 to 4 output operating-state signals OSS1 to OSS4 that indicate their own operating states. The frequency adjustment circuits FRC 1 to 4 control the frequencies of clocks CK1 to CK4 on the basis of tables T1 to T4, T30, T40, and operating-state signals OSS1 to OSS4.
摘要翻译：要解决的问题：提供能够使动力变化的负载具有性能的半导体器件。解决方案：半导体器件包括CPU核心1至4，频率调节电路FRC 1至4和时钟频率控制电路CFCC 1至4 频率调整电路FRC 1〜4包括表T1〜T4，T30，T40。频率控制电路CFCC 1〜4向CPU核心1〜4供给时钟CK1〜CK4。CPU核1〜4输出表示自身运行状态的运行状态信号OSS1〜OSS4。频率调整电路FRC 1〜4基于表T1〜T4，T30，T40以及运行状态信号OSS1〜OSS4来控制时钟CK1〜CK4的频率。

3. 发明专利

JP2013016105A Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：JP2013016105A
公开(公告)日：2013-01-24
申请号：JP2011149875
申请日：2011-07-06
申请人： Renesas Mobile Corp , ルネサスモバイル株式会社
发明人： FUJIGAYA MASAKI , IRITA TAKAHIRO
IPC分类号： G06F1/04
CPC分类号： G06F1/08 , G06F1/324 , Y02D10/126
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for achieving a stable operation.SOLUTION: A semiconductor device 1 includes: circuits 3 to 5 each of which has a predetermined function; a clock generation circuit 10 which generates a clock signal to be supplied to the circuits 3 to 5; a clock control circuit 9 which controls the clock generation circuit 10; and a notification signal generation circuit 11 which generates a notification signal NTC_SIG for performing the notification of a timing in which the clock control circuit 9 controls the clock generation circuit 10. A voltage to be supplied to the semiconductor device 1 is adjusted in response to the notification signal NTC_SIG generated by the notification signal generation circuit 11.
摘要翻译：要解决的问题：提供一种用于实现稳定操作的半导体器件。解决方案：半导体器件1包括：各自具有预定功能的电路3至5; 产生要提供给电路3至5的时钟信号的时钟产生电路10; 控制时钟发生电路10的时钟控制电路9; 以及通知信号生成电路11，其生成用于进行时钟控制电路9控制时钟生成电路10的定时的通知的通知信号NTC_SIG。响应于通知信号生成电路11生成的通知信号NTC_SIG。（C）2013，JPO＆INPIT

4. 发明专利

JP2013016104A Semiconductor device, radio communication terminal using the same, and clock frequency control method 有权
标题翻译：半导体器件，使用其的无线电通信终端和时钟频率控制方法
公开(公告)号：JP2013016104A
公开(公告)日：2013-01-24
申请号：JP2011149874
申请日：2011-07-06
申请人： Renesas Mobile Corp , ルネサスモバイル株式会社
发明人： MATSUYAMA TSUGUO , WAKAHARA KOHEI , FUJIGAYA MASAKI , IRITA TAKAHIRO
IPC分类号： G06F1/04
CPC分类号： G06F1/08 , G06F1/3225 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device suitable for a radio communication terminal and the like.SOLUTION: A semiconductor device 1 includes: a clock generation circuit 15 that changes the frequency of a clock signal to be output in response to a control signal div; an arithmetic circuit (CPU 0, for example) that operates in accordance with the clock signal; a storage circuit (IC 0, for example) that is activated in response to access from the arithmetic circuit CPU 0; a memory access detector 12 that detects the number of times of access to the storage circuit IC 0 from the arithmetic circuit CPU 0 and outputs a request signal (psreq 1, for example) when the number of times of access increases; and a clock control circuit 14 that generates the control signal div for lowering the clock signal frequency in response to the request signal psreq 1.
摘要翻译：要解决的问题：提供适合于无线电通信终端等的半导体器件。解决方案：半导体器件1包括：响应于控制信号div改变要输出的时钟信号的频率的时钟产生电路15; 算术电路（例如，CPU 0），其根据时钟信号进行动作; 响应于来自运算电路CPU 0的访问而被激活的存储电路（例如，IC 0）存储器访问检测器12，其检测从运算电路CPU0访问存储电路IC0的次数，并且当访问次数增加时输出请求信号（例如，psreq 1）; 以及时钟控制电路14，其根据请求信号psreq 1产生用于降低时钟信号频率的控制信号div。（C）2013，JPO和INPIT

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