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1. 发明专利

JP2011071441A Method of manufacturing semiconductor device, semiconductor device and wafer lamination structure 有权
标题翻译：制造半导体器件的方法，半导体器件和波形层叠结构
公开(公告)号：JP2011071441A
公开(公告)日：2011-04-07
申请号：JP2009223266
申请日：2009-09-28
申请人： Renesas Electronics Corp , Rohm Co Ltd , ルネサスエレクトロニクス株式会社 , ローム株式会社
发明人： MORIFUJI TADAHIRO , SHIMAMOTO HARUO , MIYAZAKI CHUICHI , UEMATSU SHUNEI , ABE YOSHIYUKI
IPC分类号： H01L25/065 , H01L21/301 , H01L21/304 , H01L25/07 , H01L25/18
CPC分类号： H01L24/97 , H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L21/78 , H01L23/3128 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/94 , H01L25/50 , H01L2221/68327 , H01L2224/13025 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/81193 , H01L2224/81801 , H01L2224/9202 , H01L2224/95143 , H01L2225/06513 , H01L2225/06541 , H01L2225/06582 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof, which prevent a damage of a corner part of a semiconductor chip, and also to provide a wafer lamination structure which is used for manufacturing of the semiconductor device. SOLUTION: A first semiconductor wafer W1 and a second semiconductor wafer W2 are joined keeping their surfaces faced with an underfill U held therebetween. After they are joined, a rear of the second semiconductor wafer W2 is ground. Through the grinding, the underfill U moved into a groove G2 is exposed in the rear of the semiconductor wafer W2. Thereafter, a rear of the first semiconductor wafer W1 is ground. Through the rear grinding, the underfill U moved into the groove G1 is exposed in the rear of the semiconductor wafer W1. Then, it is subjected to dicing on a dicing line L, and a semiconductor device is obtained. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件的半导体器件及其制造方法，其防止半导体芯片的角部的损坏，并且还提供用于制造半导体器件的晶片叠层结构。解决方案：将第一半导体晶片W1和第二半导体晶片W2接合，使其表面面对保持在其间的底部填充U。接合后，研磨第二半导体晶片W2的后方。通过研磨，移入槽G2的底部填充体U露出在半导体晶片W2的后部。之后，研磨第一半导体晶片W1的后方。通过后研磨，移动到槽G1中的底部填充U暴露在半导体晶片W1的后部。然后，在切割线L上进行切割，得到半导体器件。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2013157647A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013157647A
公开(公告)日：2013-08-15
申请号：JP2013108550
申请日：2013-05-23
申请人： Rohm Co Ltd , ローム株式会社
发明人： UEDA SHIGEYUKI , MORIFUJI TADAHIRO
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which inhibits the deterioration of reliability.SOLUTION: A semiconductor device includes: an electrode pad part 2 formed on an upper surface of a semiconductor substrate 1; a passivation layer 3 which includes a first opening 3a exposing an upper surface of the electrode pad part 2 and is formed on the upper surface of the semiconductor substrate 1 so as to overlap with a part of the electrode pad part 2; a barrier metal layer 5 formed on the electrode pad part 2; and a solder bump 6 formed on the barrier metal layer 5. An outer peripheral end part 5b of the barrier metal layer 5 is formed at the inner side of the first opening 3a of the passivation layer 3 in a plane view.
摘要翻译：要解决的问题：提供抑制可靠性劣化的半导体器件。解决方案：半导体器件包括：形成在半导体衬底1的上表面上的电极焊盘部分2; 钝化层3，其包括露出电极焊盘部分2的上表面的第一开口3a，并形成在半导体衬底1的上表面上以与电极焊盘部分2的一部分重叠; 形成在电极焊盘部2上的阻挡金属层5; 以及形成在阻挡金属层5上的焊料凸块6.阻挡金属层5的外周端部5b以平面图形成在钝化层3的第一开口3a的内侧。

3. 发明专利

JP2007059548A Semiconductor chip and method of manufacturing semiconductor chip 有权
标题翻译：半导体芯片和制造半导体芯片的方法
公开(公告)号：JP2007059548A
公开(公告)日：2007-03-08
申请号：JP2005241521
申请日：2005-08-23
申请人： Rohm Co Ltd , ローム株式会社
发明人： MIYATA OSAMU , MORIFUJI TADAHIRO
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/73 , H01L2224/05554 , H01L2224/16145 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip which can be correctly determined whether it is joined in parallel to a solid device such as another semiconductor chip, and a manufacturing method thereof. SOLUTION: In a slave chip 2, a connection confirming bump 13 is formed so as to lower than a functional bump 12. Accordingly, a slight inclination of surface 11 of the slave chip 2 against the surface 3 of a master chip 1 may cause a wide gap between a solder joining material 16 of a tip of the connection confirming bump 13 and the crestal plane of the connection confirming bump 7 in a portion having a wide gap between the surface 3 of the master chip 1 and the surface 11 of the slave chip 2. As a result, even if the solder joining material 16 expands, the solder joining material 16 does not reach the crestal plane of the connection confirming bump 7 and connection between the connection confirming bumps 7 and 13 cannot be realized. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供可以正确地确定其是否与诸如另一半导体芯片的固体器件并联的半导体芯片及其制造方法。解决方案：在从芯片2中，连接确认凸块13形成为低于功能凸块12.因此，从芯片2的表面11相对于主芯片1的表面3的轻微倾斜在主芯片1的表面3和表面11之间具有宽间隙的部分中，可能导致连接确认凸块13的尖端的焊料接合材料16与连接确认凸块7的凸起面之间的宽间隙结果，即使焊料接合材料16膨胀，焊料接合材料16也不会到达连接确认凸块7的凸起平面，并且不能实现连接确认凸块7和13之间的连接。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007059547A Semiconductor chip and method of manufacturing semiconductor chip 有权
标题翻译：半导体芯片和制造半导体芯片的方法
公开(公告)号：JP2007059547A
公开(公告)日：2007-03-08
申请号：JP2005241520
申请日：2005-08-23
申请人： Rohm Co Ltd , ローム株式会社
发明人： MIYATA OSAMU , MORIFUJI TADAHIRO
IPC分类号： H01L21/60
CPC分类号： H01L24/73 , H01L2224/16145 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip which can be correctly determined whether it is joined in parallel to a solid device such as another semiconductor chip, and a manufacturing method thereof. SOLUTION: A pad opening 26 is formed on a position opposite to an electrode pad 24 on a surface protective film 25 forming the uppermost layer of a slave chip 2, and the electrode pad 24 is exposed from the surface protective film 25 through the pad opening 26. A through hole 27 piercing the surface protective film 25 in a direction perpendicular to its surface 11 is provided on the peripheral edge portion of the surface protective film 25. A functional bump 12 is provided on the electrode pad 24, and projects at a predetermined projection quantity from the surface protective film 25, piercing the pad opening 26. A connection confirming bump 13 rises from the surface of an interlayer insulation film 23 facing the through hole 27, and projects from the surface protective film 25 at a projection quantity smaller than the projection quantity of the functional bump 12, piercing the through hole 27. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供可以正确地确定其是否与诸如另一半导体芯片的固体器件并联的半导体芯片及其制造方法。解决方案：在形成从芯片2的最上层的表面保护膜25上的与电极焊盘24相对的位置处形成焊盘开口26，并且电极焊盘24从表面保护膜25暴露通过衬垫开口26.在表面保护膜25的周缘部分上设置有与表面保护膜25垂直的方向刺穿表面保护膜25的通孔27.在电极焊盘24上设有功能性突起12，从表面保护膜25突出预定投影量，刺穿焊盘开口26.连接确认凸起13从层间绝缘膜23的面向通孔27的表面上升，并从表面保护膜25突出投影量小于功能凸块12的突出量，穿透通孔27.版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2008311538A Circuit board, and semiconductor device 有权
标题翻译：电路板和半导体器件
公开(公告)号：JP2008311538A
公开(公告)日：2008-12-25
申请号：JP2007159631
申请日：2007-06-18
申请人： Rohm Co Ltd , ローム株式会社
发明人： MORIFUJI TADAHIRO , UEDA SHIGEYUKI
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H05K3/3484 , H01L23/3192 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/0554 , H01L2224/1147 , H01L2224/11472 , H01L2224/11474 , H01L2224/1148 , H01L2224/13021 , H01L2224/13022 , H01L2224/13099 , H01L2224/16237 , H01L2224/73204 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H05K3/3452 , H05K2201/0191 , H05K2201/0989 , H05K2203/043 , H05K2203/0568 , H01L2224/29099
摘要： PROBLEM TO BE SOLVED: To provide a circuit board which has a semiconductor chip flip-chip mounted and has a structure such that a solder bump can be at a sufficiently large height. SOLUTION: The circuit board 1 which has the semiconductor chip flip-chip mounted has an electrode pad 3 formed on the top surface of a substrate body 2 and a solder resist layer 4 covering the top surface of the substrate body 2 and having an opening portion 4a exposing the electrode pad 3. The solder resist layer 4 is formed not in contact with the electrode pad 3 and satisfies 1.0≤H/L≤1.5, where L is the maximum width of the electrode pad and H is the thickness of the solder resist layer. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有半导体芯片倒装芯片安装的电路板，并具有使焊料凸块的高度足够大的结构。解决方案：安装有半导体芯片倒装芯片的电路板1具有形成在基板主体2的顶表面上的电极焊盘3和覆盖基板主体2的顶表面的阻焊层4，并且具有露出电极焊盘3的开口部分4.阻焊层4形成为不与电极焊盘3接触，并且满足1.0≤H/L≤1.5，其中L是电极焊盘的最大宽度，H是厚度的阻焊层。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008311531A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008311531A
公开(公告)日：2008-12-25
申请号：JP2007159354
申请日：2007-06-15
申请人： Rohm Co Ltd , ローム株式会社
发明人： MORIFUJI TADAHIRO , UEDA SHIGEYUKI
IPC分类号： H01L21/60
CPC分类号： H01L23/3192 , H01L2224/0401 , H01L2224/05022 , H01L2224/05541 , H01L2224/05552 , H01L2224/05572 , H01L2224/13005 , H01L2224/13006 , H01L2924/0002 , H01L2924/01013 , H01L2924/01022 , H01L2924/014 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing a decrease in reliability.
SOLUTION: The semiconductor device includes an electrode pad portion 2 formed on the top surface of a semiconductor substrate 1 and a first opening portion 3a exposing the top surface of the electrode pad portion 2, and also has a passivation layer 3 formed on the top surface of the semiconductor substrate 1 to overlap with a peripheral edge portion of the electrode pad portion 2, a bimetal layer 5 formed on the electrode pad portion 2 without directly contacting the passivation layer 3, and a solder bump 6 formed on the bimetal layer 5. Further, the passivation layer 3 has a step portion 3b formed by overlapping with the peripheral edge portion of the electrode pad portion 2. Further, the bimetal layer 5 has its outer peripheral end 5b formed outside the step portion 3b of the passivation layer 3 in plan view.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供能够抑制可靠性降低的半导体器件。解决方案：半导体器件包括形成在半导体衬底1的顶表面上的电极焊盘部分2和露出电极焊盘部分2的顶表面的第一开口部分3a，并且还具有形成在电极焊盘部分2上的钝化层3 半导体衬底1的顶表面与电极焊盘部分2的外围边缘部分重叠，形成在电极焊盘部分2上而不直接接触钝化层3的双金属层5和形成在双金属片上的焊料凸块6 此外，钝化层3具有通过与电极焊盘部2的周缘部重叠而形成的台阶部3b。此外，双金属层5的外周端部5b形成在钝化层的台阶部3b的外侧层3在平面图。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2007184654A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007184654A
公开(公告)日：2007-07-19
申请号：JP2007101783
申请日：2007-04-09
申请人： Rohm Co Ltd , ローム株式会社
发明人： TANIDA KAZUMA , MORIFUJI TADAHIRO , MIYATA OSAMU
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/48091 , H01L2224/48227 , H01L2224/73267 , H01L2924/181 , H01L2924/18162 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a size of chip size and comprises a multichip module. SOLUTION: The semiconductor device 21 includes a first semiconductor chip 3 which possesses a first functional surface 3F wherein a first functional device 3a is formed, and a first backside 3R opposite to the first functional surface 3F; and a second semiconductor chip 2 which possesses a second functional surface 2F wherein a second functional device 2a is formed. The second functional surface 2F has a region opposite to the first functional surface 3F and a non-countering region 7 not opposite to the first functional surface 3F. An insulating film 22 is formed continuously so as to cover the non-countering region 7 and the first backside 3R of the first semiconductor chip 3. Rewiring 9 electrically connected to the second functional device 2 is formed on the surface of the insulating film 22, a protective resin 12 is arranged so as to cover the rewiring 9. The protective resin 12 is penetrated from the rewiring 9 so that external connection terminals 10 are set up vertically. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种尺寸为芯片尺寸并包括多芯片模块的半导体器件。解决方案：半导体器件21包括第一半导体芯片3，其具有形成有第一功能器件3a的第一功能面3F和与第一功能面3F相反的第一背面3R; 以及具有形成第二功能元件2a的第二功能面2F的第二半导体芯片2。第二功能面2F具有与第一功能面3F相对的区域和与第一功能面3F不相对的非对置区域7。连续地形成绝缘膜22，以覆盖第一半导体芯片3的非对抗区域7和第一背面3R。在绝缘膜22的表面上形成与第二功能元件2电连接的重叠9，布置保护树脂12以覆盖重新布线9.保护树脂12从重新布线9穿透，使得外部连接端子10垂直地设置。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006005101A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006005101A
公开(公告)日：2006-01-05
申请号：JP2004178756
申请日：2004-06-16
申请人： Rohm Co Ltd , ローム株式会社
发明人： TANIDA KAZUMA , MORIFUJI TADAHIRO , MIYATA OSAMU
IPC分类号： H01L25/18 , H01L23/12 , H01L23/31 , H01L25/065 , H01L25/07
CPC分类号： H01L25/0657 , H01L23/3114 , H01L24/20 , H01L24/48 , H01L24/82 , H01L2224/04105 , H01L2224/05001 , H01L2224/05023 , H01L2224/05124 , H01L2224/05147 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/12105 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73209 , H01L2224/73265 , H01L2224/73267 , H01L2225/06513 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a size of chip size and comprises a multichip module. SOLUTION: The semiconductor device 21 includes a first semiconductor chip 3 which possesses a first functional surface 3F wherein a first functional device 3a is formed, and a first rear surface 3R opposite to the first functional surface 3F; and a second semiconductor chip 2 which possesses a second functional surface 2F wherein a second functional device 2a is formed. The second functional surface 2F has a region opposite to the first functional surface 3F and a non-countering region 7 not opposite to the first functional surface 3F. An insulating film 22 is formed continuously so as to cover the non-countering region 7 and the first rear surface 3R of the first semiconductor chip 3. Rewiring 9 electrically connected to the second functional device 2 is formed on the surface of the insulating film 22, a protective regin 12 is arranged so as to cover the rewiring 9. The protective regin 12 is penetrated from the rewiring 9 so that external connection terminals 10 are set up vertically. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种尺寸为芯片尺寸并包括多芯片模块的半导体器件。解决方案：半导体器件21包括第一半导体芯片3，其具有形成第一功能器件3a的第一功能表面3F和与第一功能表面3F相对的第一后表面3R; 以及具有形成第二功能元件2a的第二功能面2F的第二半导体芯片2。第二功能面2F具有与第一功能面3F相对的区域和与第一功能面3F不相对的非对置区域7。连续地形成绝缘膜22，以覆盖第一半导体芯片3的不对抗区域7和第一后表面3R。在绝缘膜22的表面上形成有与第二功能元件2电连接的重合9 设置保护性回收器12以覆盖重新布线9.保护回收器12从重新布线9穿透，使得外部连接端子10垂直地设置。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2008311530A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008311530A
公开(公告)日：2008-12-25
申请号：JP2007159351
申请日：2007-06-15
申请人： Rohm Co Ltd , ローム株式会社
发明人： UEDA SHIGEYUKI , MORIFUJI TADAHIRO
IPC分类号： H01L21/60
CPC分类号： H01L23/3192 , H01L2224/0401 , H01L2224/05022 , H01L2224/05541 , H01L2224/05555 , H01L2224/05558 , H01L2224/05559 , H01L2224/05563 , H01L2224/05571 , H01L2224/05572 , H01L2224/13005 , H01L2224/13006 , H01L2924/01013 , H01L2924/01022 , H01L2924/014 , H01L2924/207 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing reliability from being deteriorated. SOLUTION: The semiconductor device includes an electrode pad 2 formed on the top surface of a semiconductor substrate 1 and a first opening 3a that exposes the top surface of the electrode pad 2, and comprises, on the top surface of the semiconductor substrate 1, a passivation layer 3 formed so as to partially overlap the electrode pad 2, a barrier metal layer 5 formed on the electrode pad 2, and a solder bump 6 formed on the barrier metal layer 5. The outer circumferential end 5b of the barrier metal layer 5 is formed inside the first opening 3a of the passivation layer 3 in a planar view. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供能够抑制可靠性劣化的半导体器件。解决方案：半导体器件包括形成在半导体衬底1的顶表面上的电极焊盘2和暴露电极焊盘2的顶表面的第一开口3a，并且包括在半导体衬底的顶表面上如图1所示，形成为与电极焊盘2部分重叠的钝化层3，形成在电极焊盘2上的阻挡金属层5和形成在阻挡金属层5上的焊料凸块6。在平面图中，在钝化层3的第一开口3a内形成金属层5。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2007165631A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007165631A
公开(公告)日：2007-06-28
申请号：JP2005360590
申请日：2005-12-14
申请人： Rohm Co Ltd , ローム株式会社
发明人： MIYATA OSAMU , MORIFUJI TADAHIRO
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/16145 , H01L2224/32145 , H01L2224/48247 , H01L2224/73204 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing deformation of semiconductor chips due to unevenness of a stress, and smoothly injecting a resin for sealing between both the semiconductor chips.
SOLUTION: A chip joining region to which a slave chip 2 is joined is set on the center portion of a surface 3 of a master chip 1, and a plurality of bumps 6 are arranged with appropriate intervals in the chip joining region. Also, a plurality of pads 11 for external connection are arranged with an interval on the external peripheral portion of the surface 3 of the master chip 1. The pads 11 for external connection are each electrically connected to an internal circuit formed in the chip connection region of the master chip 1, and a protective element 14 for preventing input of a surge from the pads 11 for external connection is provided between each of the pads 11 for external connection and the internal circuit. On the other hand, a plurality of pumps 22 are arranged on positions opposite to each of bumps 6 of the master chip 1 on the surface of the slave chip 2.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供能够防止由于应力不均匀引起的半导体芯片变形的半导体器件，并且平滑地注入两个半导体芯片之间用于密封的树脂。解决方案：将芯片2接合的芯片接合区域设置在主芯片1的表面3的中心部分，并且在芯片接合区域中以适当间隔布置多个凸块6。此外，用于外部连接的多个焊盘11以主间隔件1的表面3的外围部分间隔布置。外部连接用焊盘11分别电连接到芯片连接区域中形成的内部电路并且在每个用于外部连接的焊盘11和内部电路之间设置用于防止从用于外部连接的焊盘11的浪涌输入的保护元件14。另一方面，在副芯片2的表面上，与主芯片1的凸块6相对的位置配置有多个泵22.副本（C）2007，JPO＆INPIT

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