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1. 发明专利

JP2014089664A Skew adjustment circuit, and optical disk drive 审中-公开
标题翻译： SKEW调整电路和光盘驱动器
公开(公告)号：JP2014089664A
公开(公告)日：2014-05-15
申请号：JP2012240531
申请日：2012-10-31
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： KATO TAKAHIRO
IPC分类号： G06F1/06 , G11B20/10 , G11B20/14
摘要： PROBLEM TO BE SOLVED: To make a skew adjustment of a polyphase clock signal which is applicable to high-speed recording of an optical disk drive.SOLUTION: A skew adjustment circuit is provided with a first delay circuit (303) for delaying a first clock signal; a second delay circuit (301) for delaying a second clock signal; and a third delay circuit (302) for delaying a third clock signal in an intermediate phase between the first clock signal and second clock signal. Further, the skew adjustment circuit is provided with a first logic gate (304) which exclusive ORs the output of the first delay circuit and the output of the third delay circuit, and a second logic gate (305) which exclusive ORs the output of the second delay circuit and the output of the third delay circuit. The skew adjustment circuit is provided with a feedback path (FBR) for supplying a feedback voltage for adjusting a delay time of the third delay circuit based upon the difference between the output of the first logic gate and the output of the second logic gate to the third delay circuit, and makes a skew adjustment of a polyphase clock signal.
摘要翻译：要解决的问题：对适用于光盘驱动器的高速记录的多相时钟信号进行偏斜调整。解调：偏斜调整电路设置有用于延迟第一时钟的第一延迟电路（303）信号; 用于延迟第二时钟信号的第二延迟电路（301）; 以及用于在第一时钟信号和第二时钟信号之间的中间相位延迟第三时钟信号的第三延迟电路（302）。此外，该偏斜调整电路设置有第一逻辑门（304），其将第一延迟电路的输出与第三延迟电路的输出进行异或运算，第二逻辑门（305）将与第二延迟电路和第三延迟电路的输出。偏斜调整电路设置有反馈路径（FBR），用于提供反馈电压，用于基于第一逻辑门的输出和第二逻辑门的输出与第二逻辑门的输出之间的差异来调整第三延迟电路的延迟时间第三延迟电路，并且进行多相时钟信号的偏斜调整。

2. 发明专利

JP2011166401A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2011166401A
公开(公告)日：2011-08-25
申请号：JP2010026253
申请日：2010-02-09
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： KATO TAKAHIRO
IPC分类号： H03K3/354 , H03K3/0231
CPC分类号： H03F3/45183 , H03F2203/45481
摘要： PROBLEM TO BE SOLVED: To achieve a proper oscillation operation and expand the range of oscillation frequency variation, concerning a ring oscillator circuit. SOLUTION: The ring oscillator circuit includes, for instance, a plurality of differential amplifier circuits DAMP_As. MOS transistors (MN_LIM1 and MN_LIM2) are added to input nodes (IT and IB) of a differential pair (MN1 and NM2) of the DAMP_As, respectively. Further, gate control circuits GCTL_T, GCTL_B are incorporated to control the gates of the transistors, respectively. The GCTL_T, GCTL_B cause the MN_LIM1, 2 to function as an amplitude limiter circuit in mode 3, exercise control to turn off the limiter circuit in mode 2, and use the limiter circuit to start oscillation in mode 1. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：关于环形振荡器电路，实现适当的振荡操作并扩大振荡频率变化的范围。解决方案：环形振荡器电路包括例如多个差分放大器电路DAMP_As。 MOS晶体管（MN_LIM1和MN_LIM2）分别被添加到DAMP_As的差分对（MN1和NM2）的输入节点（IT和IB）。此外，并入栅极控制电路GCTL_T，GCTL_B以分别控制晶体管的栅极。 GCTL_T，GCTL_B使模式3中的MN_LIM1,2作为限幅电路，进行模式2中的限制电路的运行控制，并使用限幅电路在模式1中开始振荡。版权所有（C） C）2011，JPO＆INPIT

3. 发明专利

JP2012205046A Semiconductor integrated circuit and method of operating the same 审中-公开
标题翻译：半导体集成电路及其工作方法
公开(公告)号：JP2012205046A
公开(公告)日：2012-10-22
申请号：JP2011067266
申请日：2011-03-25
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： KATO TAKAHIRO
IPC分类号： H03L7/093
CPC分类号： H03L7/097 , H03L7/0891 , H03L7/091 , H03L7/1974
摘要： PROBLEM TO BE SOLVED: To reduce characteristic variations of a PLL circuit due to variations in element size of transistors and reduce increase in circuit scale and power consumption when employing an on-chip loop filter.SOLUTION: A semiconductor integrated circuit incorporates a phase-locked loop circuit comprising a phase/frequency comparator 1, a loop attenuator 2, a charge pump 3, a loop filter 4, a voltage-controlled oscillator 5 and a frequency divider 6. The attenuator 2 includes a sampling circuit 21 and a counter 22. A sampling pulse SPL_CLK and first and second output signals output from the phase/frequency comparator 1 are supplied to the circuit 21, which in turn outputs a sampling output signal. When completing counting up a predetermined number of sampling pulses output from the circuit 21, the counter 22 outputs a count completion output signal. The charge pump 3 outputs a charge current or discharge current to the loop filter 4 in response to the count completion output signal.
摘要翻译：要解决的问题：为了减少由于晶体管的元件尺寸的变化引起的PLL电路的特性变化，并且当采用片上环路滤波器时减小电路规模和功耗的增加。解决方案：半导体集成电路包括锁相环电路，该锁相环电路包括相/频比较器1，环路衰减器2，电荷泵3，环路滤波器4，压控振荡器5和分频器6 衰减器2包括采样电路21和计数器22.采样脉冲SPL_CLK和从相位/频率比较器1输出的第一和第二输出信号被提供给电路21，电路21又输出采样输出信号。当从电路21输出的预定数量的采样脉冲完成计数时，计数器22输出计数完成输出信号。电荷泵3响应于计数完成输出信号而向环路滤波器4输出充电电流或放电电流。版权所有（C）2013，JPO＆INPIT

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