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1. 发明专利

JP2014146829A Semiconductor chip and semiconductor device 审中-公开
标题翻译：半导体芯片和半导体器件
公开(公告)号：JP2014146829A
公开(公告)日：2014-08-14
申请号：JP2014078133
申请日：2014-04-04
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： ABE YOSHIYUKI , MIYAZAKI CHUICHI , MUTO HIDEO , TONO TOMOKO
IPC分类号： H01L21/301
摘要： PROBLEM TO BE SOLVED: To reduce or prevent defect in shape caused by cutting in a disconnection process of a semiconductor wafer using stealth dicing.SOLUTION: In the case of dividing a semiconductor wafer 1W by stealth dicing, pads 1LBt for testing of a cutting region CR and an alignment target Am are arranged on one side of the cutting region CR in a width direction, and laser beams for forming a modified region PR are irradiated on a position away from the pads 1LBt for testing and the alignment target Am in planar view. By doing this, defect in shape caused by cutting in a disconnection process of the semiconductor wafer using stealth dicing can be reduced or prevented.
摘要翻译：要解决的问题：为了减少或防止使用隐形切割在半导体晶片的断开过程中切割造成的形状缺陷。解决方案：在通过隐形切割分割半导体晶片1W的情况下，用于测试切割区域的焊盘1LBt CR和对准目标Am布置在切割区域CR的宽度方向的一侧上，并且用于形成修改区域PR的激光束照射在远离用于测试的焊盘1LBt的位置和平面图中的对准目标Am 。通过这样做，可以减少或防止使用隐形切割在半导体晶片的断开过程中切割引起的形状缺陷。

2. 发明专利

JP2014007351A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2014007351A
公开(公告)日：2014-01-16
申请号：JP2012143697
申请日：2012-06-27
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： KITAICHI YUKIHIRO , MIYAZAKI CHUICHI , ABE YOSHIYUKI
IPC分类号： H01L21/301
摘要： PROBLEM TO BE SOLVED: To solve various problems associated, as found by the inventors of the present application, with the use in mass production of a wafer thinning and pelletizing process which, in response to the demand for further reduction in chip thickness, combines a dicing-preceded pelletization process or DBG process and a plasma etching based dicing groove internal stress relief process.SOLUTION: The outline of one embodiment of the present application is such that when carrying out a dicing-preceded pelletization process in a semiconductor device manufacturing method, a half-cut groove is formed while the surface is covered with a protective film and stresses are relieved from the side faces of the groove. Then, BG tape is pasted to the surface and the reverse side is polished before the reverse side is fixed with chip retention tape, after which the BG tape is removed.
摘要翻译：要解决的问题：为了解决本发明的发明人所发现的与本发明的发明人相关的各种问题，在大量生产晶片薄化和造粒工艺中，根据对芯片厚度的进一步降低的需求，将切割之前的造粒工艺或DBG工艺以及基于等离子体蚀刻的切割槽内部应力消除工艺。本申请的一个实施例的轮廓使得当在半导体器件制造方法中进行切割前的造粒工艺时，在表面被保护膜覆盖的同时形成半切槽，并且从槽的侧面释放应力。然后，将BG带粘贴到表面，并且在反向侧用芯片保持带固定之前将反面进行抛光，之后除去BG带。

3. 发明专利

JP2013120767A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2013120767A
公开(公告)日：2013-06-17
申请号：JP2011266644
申请日：2011-12-06
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , Rohm Co Ltd , ローム株式会社
发明人： KITAICHI YUKIHIRO , SHIMAMOTO HARUO , MIYAZAKI CHUICHI , ABE YOSHIYUKI , UEMATSU SHUNEI , YASUNAGA SHOJI
IPC分类号： H01L21/301 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device.SOLUTION: A semiconductor device manufacturing method comprises: forming a groove 10e in scribe regions 10d of a wafer (semiconductor wafer) 10 from a surface 3a side by a chemical reaction treatment (etching treatment); and grinding a rear face 10b on the side opposite to the surface 3a after forming the groove 10e, to isolate a plurality of chip regions 10c arranged among the scribe regions 10d. In this method, a metal pattern 3f is formed on the surface 3a of the scribe region 10d. In the step of forming the groove 10e, the metal pattern 3f is not removed but remains.
摘要翻译：要解决的问题：提高半导体器件的可靠性。解决方案：半导体器件制造方法包括：通过化学反应处理（蚀刻处理）从表面3a侧在晶片（半导体晶片）10的划线区域10d中形成沟槽10e; 在形成槽10e之后，在与表面3a相反的一侧研磨后表面10b，以隔离划线区域10d之间布置的多个芯片区域10c。在该方法中，在刻划区域10d的表面3a上形成金属图案3f。在形成槽10e的步骤中，金属图案3f不被去除而残留。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2012146892A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012146892A
公开(公告)日：2012-08-02
申请号：JP2011005546
申请日：2011-01-14
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： ABE YOSHIYUKI , MIYAZAKI CHUICHI , UEMATSU SHUNEI , SHIMAMOTO HARUO
IPC分类号： H01L21/301 , H01L21/304 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/3121 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05124 , H01L2224/05554 , H01L2224/0557 , H01L2224/05582 , H01L2224/05644 , H01L2224/05655 , H01L2224/06181 , H01L2224/13022 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/48644 , H01L2224/48655 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2224/85203 , H01L2224/85205 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2225/06568 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/01032 , H01L2924/3512
摘要： PROBLEM TO BE SOLVED: To suppress the lowering of the strength of a semiconductor device.SOLUTION: The method comprises: a step (a) in which a surface 3a, a plurality of chip regions 10c formed on the surface 3a, dicing regions formed between chip regions 10c, and a surface 3a of a wafer ( semiconductor wafer ) 10 having a rear surface opposite to the surface 3a are fixed to a supporting member 15; a step (b) in which the rear surface of the wafer 10 is ground and the rear surface 3b is exposed in the state that the wafer 10 is fixed to the supporting member 15; a step (c) in which the wafer 10 is divided for each chip region 10c in the state that the wafer 10 is fixed to the supporting member 15; a step (d) in which a side surface 3c of the chip region 10c is etched, a crushed layer formed on the side surface 3c by the step (c) is removed, and a plurality of semiconductor chips are formed; and a step (e) in which, after the step (d), a plurality of divided chip regions 10c are removed from the supporting member 15 to obtain a plurality of semiconductor chips.
摘要翻译：要解决的问题：为了抑制半导体器件的强度的降低。解决方案：该方法包括：步骤（a），其中表面3a，形成在表面3a上的多个芯片区域10c，形成在芯片区域10c之间的切割区域和晶片的表面3a（半导体晶片）10具有与表面3a相对的后表面固定到支撑构件15; 在晶片10的后表面被研磨并且在晶片10固定到支撑构件15的状态下暴露后表面3b的步骤（b）; 在晶片10被固定到支撑部件15的状态下，对于每个芯片区域10c分割晶片10的步骤（c）去除了芯片区域10c的侧面3c被蚀刻的步骤（d），通过步骤（c）形成在侧表面3c上的破碎层，形成多个半导体芯片; 以及步骤（e），其中在步骤（d）之后，从支撑构件15移除多个分割的芯片区域10c以获得多个半导体芯片。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2011135102A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011135102A
公开(公告)日：2011-07-07
申请号：JP2011063771
申请日：2011-03-23
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： TONO TOMOKO , MIYAZAKI CHUICHI , ABE YOSHIYUKI
IPC分类号： H01L25/065 , H01L21/52 , H01L25/07 , H01L25/18
CPC分类号： H01L24/27 , H01L24/73 , H01L24/743 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/743 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/48145
摘要： PROBLEM TO BE SOLVED: To provide a thin semiconductor having chips stacked in multi-stages. SOLUTION: A reformed region PL is formed by irradiating a semiconductor substrate 1S of a semiconductor wafer 1W with laser light having its condensing point inside the semiconductor substrate 1S. After a reverse surface of the semiconductor wafer 1W is subsequently coated with a liquid adhesive by a rotary coating method, the adhesive is dried to form a solid adhesive layer 8a. Then the semiconductor wafer 1W is divided into individual semiconductor chips based upon the reformed region PL as a division starting point. A semiconductor chip is bonded onto a principal surface of another semiconductor chip with an adhesive layer 8a on the reverse surface thereof to manufacture a semiconductor device having the semiconductor chips stacked in multi-stages. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供具有以多级堆叠的芯片的薄半导体。解决方案：通过用半导体衬底1S内的聚光点的激光照射半导体晶片1W的半导体衬底1S来形成重整区PL。在通过旋转涂覆方法随后用液体粘合剂涂覆半导体晶片1W的反面后，将粘合剂干燥以形成固体粘合剂层8a。然后，基于重整区域PL将半导体晶片1W分割成单独的半导体芯片作为分割起始点。半导体芯片在其另一半导体芯片的主表面上粘接有粘合剂层8a，以制造半导体芯片，该半导体器件具有多级堆叠的半导体芯片。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010287592A Semiconductor device, semiconductor wafer, and method of manufacturing the same 审中-公开
标题翻译：半导体器件，半导体器件及其制造方法
公开(公告)号：JP2010287592A
公开(公告)日：2010-12-24
申请号：JP2009137893
申请日：2009-06-09
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： NAKA YASUHIRO , TANAKA TADAYOSHI , UEMATSU SHUNEI , MIYAZAKI CHUICHI , SUZUKI KAZUNARI , NAKAJIMA YASUYUKI , ABE YOSHIYUKI , TAKATSU KENJI , KITAICHI YUKIHIRO , OKANE SHINYA
IPC分类号： H01L21/304 , H01L21/301 , H01L21/3205 , H01L21/60 , H01L23/52
CPC分类号： H01L24/11 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05571 , H01L2224/05644 , H01L2224/06102 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01052 , H01L2924/01055 , H01L2924/01056 , H01L2924/01064 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10158 , H01L2924/1306 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/05552 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of suppressing the occurrence of cracks in a diced semiconductor chip, when dicing a semiconductor wafer in which a bump electrode is formed in each chip region into individual semiconductor chips. SOLUTION: A groove DT is formed on the back of a semiconductor wafer WF with an adhesive tape AT pasted to the main surface of the semiconductor wafer WF. In order to form the groove DT on the back of the semiconductor wafer WF, after applying a resist film on the back of the semiconductor wafer WF, the resist film is patterned by using photolithography technology. The resist film is patterned so that no resist film remains in a region for forming the groove DT. The groove DT is formed in the prescribed region of the semiconductor wafer WF by dry-etching technology using the patterned resist film as a mask. Concretely, the groove DT is formed in a region in the vicinity of a dicing line DL. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供能够抑制切割的半导体芯片中的裂纹的发生的技术，当将在每个芯片区域中形成凸起电极的半导体晶片切割成单独的半导体芯片时。解决方案：在半导体晶片WF的背面上形成凹槽DT，其中粘合带AT粘贴到半导体晶片WF的主表面。为了在半导体晶片WF的背面上形成沟槽DT，在半导体晶片WF的背面上涂覆抗蚀剂膜之后，通过使用光刻技术对抗蚀剂膜进行构图。抗蚀剂膜被图案化，使得在用于形成凹槽DT的区域中不存在抗蚀剂膜。通过使用图案化的抗蚀剂膜作为掩模的干蚀刻技术，在半导体晶片WF的规定区域中形成凹槽DT。具体地说，槽DT形成在切割线DL附近的区域。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2014187302A Method of manufacturing electronic component and electronic component manufacturing system 审中-公开
标题翻译：制造电子元件和电子元件制造系统的方法
公开(公告)号：JP2014187302A
公开(公告)日：2014-10-02
申请号：JP2013062446
申请日：2013-03-25
申请人： Rohm Co Ltd , ローム株式会社 , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： YASUNAGA SHOJI , SHIMAMOTO HARUO , MIYAZAKI CHUICHI , ABE YOSHIYUKI , KITAICHI YUKIHIRO
IPC分类号： H01L21/52 , H01L21/301 , H01L21/683
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic component, in which improvement of efficiency in manufacturing an electronic component is promoted.SOLUTION: A method of manufacturing an electronic component uses an intermediate product 3 containing a plurality of functional chips 31, and a bond body 32 to which the plurality of functional chips 31 are bonded. The plurality of functional chips 31 respectively include a first chip main surface 311 and a second chip main surface 312, looking at an opposite side from each other. At the intermediate product 3, the second chip main surface 312 of each of the plurality of functional chips 31 is bonded to the bond body 32. The method includes a step in which the intermediate product 3 is held by a holding stage 1 in a condition in which the first chip main surface 311 of each of the plurality of functional chips 31 abuts with the holding stage 1, and a step in which the bond body 32 is removed from the second chip main surface 312 of each of the plurality of function chips 31. The step for removing the bond body 32 is performed in a condition in which the function chip 31 is held by the holding stage 1.
摘要翻译：要解决的问题：提供一种电子部件的制造方法，其中提高了电子部件制造的效率。解决方案：一种制造电子部件的方法使用包含多个功能芯片31的中间产品3，以及键合体，多个功能芯片31接合到该粘结体32。多个功能芯片31分别包括彼此相对的第一芯片主表面311和第二芯片主表面312。在中间产品3中，多个功能芯片31中的每一个的第二芯片主表面312结合到粘结体32.该方法包括以下步骤：中间产品3由保持台1保持在条件其中，多个功能芯片31的每一个的第一芯片主表面311与保持台1邻接，并且将粘合体32从多个功能芯片的每一个的第二芯片主表面312移除的步骤在功能芯片31被保持台1保持的状态下进行去除接合体32的步骤。

8. 发明专利

JP2014093392A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014093392A
公开(公告)日：2014-05-19
申请号：JP2012242538
申请日：2012-11-02
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： SAITO SHIGEAKI , SHIMAMOTO HARUO , MIYAZAKI CHUICHI , ABE YOSHIYUKI , KITAICHI YUKIHIRO
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/13 , H01L2224/16145 , H01L2225/06562 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/15788 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To suppress or prevent a fluctuation in the electrical characteristics of a semiconductor device having a through electrode.SOLUTION: In a semiconductor substrate SS, a through hole THs is formed, which penetrates between a first surface and a second surface that is on the back side of the first surface. A through electrode TVp is formed in the through hole THs. The through electrode TVp is formed by embedding a main conductor film M on the small diameter side of the through hole THs so as to form a hollow portion HS on the large diameter side of the through hole THs. An insulator film R made of resin or the like is embedded into the hollow portion HS. This structure allows stress caused by thermal expansion of the through electrode TVp to escape to the insulator film R that is softer than the semiconductor substrate SS. As a result, the stress applied from the through electrode TVp to the semiconductor substrate SS can be relaxed, and a fluctuation in the electrical characteristics of a MOSFETQ (Metal Oxide Semiconductor Field Effect Transistor) formed in the semiconductor substrate SS can be suppressed or prevented.
摘要翻译：要解决的问题：抑制或防止具有通孔的半导体器件的电特性的波动。解决方案：在半导体衬底SS中，形成穿透在第一表面和第二表面之间的通孔TH，位于第一表面的背面。贯通电极TVp形成在通孔THs中。通孔电极TVp是通过在通孔THs的小直径侧嵌入主导体膜M而形成的，以便在通孔THs的大直径侧形成中空部HS。由树脂等制成的绝缘膜R嵌入中空部HS。该结构允许通过电极TVp的热膨胀引起的应力逸出到比半导体衬底SS软的绝缘膜R. 结果，能够缓和从贯通电极TVp施加到半导体基板SS的应力，能够抑制或阻止在半导体基板SS中形成的MOSFETQ（金属氧化物半导体场效应晶体管）的电特性的波动。

9. 发明专利

JP2014075487A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014075487A
公开(公告)日：2014-04-24
申请号：JP2012222294
申请日：2012-10-04
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： SAITO SHIGEAKI , SHIMAMOTO HARUO , MIYAZAKI CHUICHI , ABE YOSHIYUKI , KITAICHI YUKIHIRO
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress or prevent changes in electrical characteristics of a semiconductor device having a through electrode.SOLUTION: On a semiconductor substrate SS constituting a logic chip LC, a through electrode TVA, which penetrates a first surface and a second surface that is on a backside thereof, is formed. The through electrode TVA is constituted of: a main conductor film MM that is formed of Cu; and a barrier metal BM that is provided so as to cover an outer periphery of the main conductor film MM to prevent diffusion of the Cu. Further, on a part of the semiconductor SS on a side surface of a through hole THA where the through electrode TVA is provided, a gettering site GSB for capturing the Cu and other heavy metal elements is formed. Accordingly, even when a pin hole or the like is generated in the barrier metal BM, the Cu of the main conductor film MM of the through electrode TVA can be captured by the gettering site GSB, thereby allowing changes in electrical characteristics of an element due to diffusion of the Cu to be suppressed or prevented.
摘要翻译：要解决的问题：抑制或防止具有贯通电极的半导体器件的电特性的变化。解决方案：在构成逻辑芯片LC的半导体衬底SS上，穿透第一表面和第二表面的贯通电极TVA，形成在其背面。贯通电极TVA由以下部分构成：由Cu形成的主导体膜MM; 以及阻挡金属BM，其设置成覆盖主导体膜MM的外周，以防止Cu的扩散。此外，在设置贯通电极TVA的通孔THA的侧面的半导体SS的一部分上形成有用于捕获Cu等重金属元素的吸杂位点GSB。因此，即使在阻挡金属BM中产生针孔等的情况下，通过电极TVA的主导体膜MM的Cu也可以被吸杂位点GSB捕获，从而允许元件的电特性的变化以抑制或防止Cu的扩散。

10. 发明专利

JP2013080972A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2013080972A
公开(公告)日：2013-05-02
申请号：JP2013019218
申请日：2013-02-04
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： ABE YOSHIYUKI , MIYAZAKI CHUICHI , MUTO HIDEO , TONO TOMOKO
IPC分类号： H01L21/301 , B23K26/38 , B23K26/40
摘要： PROBLEM TO BE SOLVED: To reduce or prevent failures in a cutting shape, in cutting processing of a semiconductor wafer using stealth dicing.SOLUTION: In the case that a semiconductor wafer 1W is divided by stealth dicing, a pad 1LBt for testing and an alignment target Am in a cutting region CR are brought and arranged near one side in a width direction of the cutting region CR, and a laser beam for forming a modification region PR is emitted onto a position distant in a plane from the pad 1LBt for testing and the alignment target Am. Thereby, in cutting processing of the semiconductor wafer using stealth dicing, failures in a cutting shape can be reduced or prevented.
摘要翻译：要解决的问题：为了减少或防止切割形状的故障，在使用隐形切割的半导体晶片的切割加工中。解决方案：在通过隐形切割分割半导体晶片1W的情况下，在切割区域CR的宽度方向上的一侧附近设置用于测试的焊盘1LBt和切割区域CR中的对准目标Am 并且用于形成修改区域PR的激光束被发射到与用于测试的焊盘1LBt和对准目标Am的平面中的远离的位置。因此，在使用隐形切割的半导体晶片的切割处理中，可以减少或防止切割形状的故障。版权所有（C）2013，JPO＆INPIT

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