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1. 发明专利

JP2013081190A Systems and methods for implementing cyclic redundancy checks 审中-公开
标题翻译：用于实施循环冗余检查的系统和方法
公开(公告)号：JP2013081190A
公开(公告)日：2013-05-02
申请号：JP2012250168
申请日：2012-11-14
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： STEELE BRIAN , WILEY GEORGE A
IPC分类号： H04L1/24 , H04L1/00
CPC分类号： H04L7/10 , G09G5/006 , G09G2370/045 , G09G2370/10 , H04L7/048
摘要： PROBLEM TO BE SOLVED: To provide systems and methods for implementing cyclic redundancy checks to exchange system error information.SOLUTION: A CRC generator system intentionally corrupts CRC values to transmit system error information, and includes a CRC generator, a CRC corrupter, an error detector and an error value generator. A digital transmission link is an MDDI link.
摘要翻译：要解决的问题：提供用于实施循环冗余检查以交换系统错误信息的系统和方法。解决方案：CRC发生器系统有意地破坏CRC值以传输系统错误信息，并且包括CRC发生器，CRC腐蚀器，误差检测器和误差值发生器。数字传输链路是MDDI链路。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2010226725A High-speed data rate interface device and method 有权
标题翻译：高速数据速率接口设备和方法
公开(公告)号：JP2010226725A
公开(公告)日：2010-10-07
申请号：JP2010089293
申请日：2010-04-08
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： ANDERSON JON JAMES , STEELE BRIAN , WILEY GEORGE A , SHEKHAR SHASHANK
IPC分类号： H04L25/02 , G06F13/38 , H04J3/00 , H04J3/24 , H04L12/28 , H04L12/56 , H04L12/64 , H04L29/00 , H04L29/06 , H04L29/08 , H04M1/00 , H04M1/725
CPC分类号： H04L12/6418 , H04L29/06027 , H04L65/1069 , H04L65/4069 , H04L65/80 , H04L67/125 , H04L67/36 , H04L69/329 , H04L2012/6483 , H04M1/72527 , Y02D70/144 , Y02D70/26
摘要： PROBLEM TO BE SOLVED: To provide a data interface for transferring digital data between a host and a client on a communication channel, with the use of a packet structure linked together, for the sake of forming communication protocols used for communicating a pre-selected set of digital control data and digital presentation data. SOLUTION: Signal protocols are structured so as to produce, transmit and receive packets for forming communication protocols and then form digital data into one or more types of data packets. At least one is resident in a host device to be used by a link controller linked with the client through the communication channel. The interface comes to act as a highly-cost-effective, low-power-consuming, bidirectional, and high-speed data transferring mechanism in a short-"serial"-type data link. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了形成用于传送预先通信的通信协议，为了提供用于在通信信道上的主机和客户端之间传送数字数据的数据接口，使用连接在一起的分组结构 - 选择的数字控制数据和数字演示数据集。信号协议被构造为产生，发送和接收用于形成通信协议的分组，然后将数字数据形成为一种或多种类型的数据分组。至少一个驻留在主机设备中，以由通过通信信道与客户端链接的链路控制器使用。该接口在短期“串行”型数据链路中起着高成本效益，低功耗，双向和高速数据传输机制的作用。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2010011480A High data rate interface 有权
标题翻译：高数据速率接口
公开(公告)号：JP2010011480A
公开(公告)日：2010-01-14
申请号：JP2009209851
申请日：2009-09-10
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： ANDERSON JON JAMES , STEELE BRIAN , WILEY GEORGE A , SHEKHAR SHASHANK
IPC分类号： H04L29/06 , H04L12/28 , H04L12/40 , H04L12/56 , H04L12/64 , H04L29/08 , H04M1/725
CPC分类号： H04L12/40052 , H04L47/283 , H04L65/608 , H04L69/03 , H04L69/10 , H04L69/18 , H04L69/323 , H04L69/324 , H04M1/72527 , Y02D70/12 , Y02D70/122 , Y02D70/144 , Y02D70/26
摘要： PROBLEM TO BE SOLVED: To provide a data digital interface for transferring digital data between a host device and a client device at high speed. SOLUTION: A data interface is for transferring the digital data between a host 202 and a client 204 over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control data and digital presentation data. A signal protocol is used by link controllers which are configured to generate, transmit, and receive a packet forming the communication protocol and to form the digital data into one or more types of data packets. At least one link controller resides always at the host device. The link controllers are coupled to the client 204 through the communication path, The interface provides a cost-effective, low power, bi-directional, and high-speed data transfer mechanism over a short-range "serial" type data link. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在主机设备和客户端设备之间高速传输数字数据的数据数字接口。解决方案：数据接口用于通过链路连接在一起的分组结构通过通信路径在主机202和客户端204之间传送数字数据，以形成通信协议，用于传送预先选择的一组数字控制数据和数字呈现数据。链路控制器使用信号协议，链路控制器被配置为生成，发送和接收形成通信协议的分组，并将数字数据形成为一种或多种类型的数据分组。至少一个链路控制器始终位于主机设备上。链路控制器通过通信路径耦合到客户端204.该接口通过短距离“串行”类型数据链路提供了具有成本效益的低功率，双向和高速数据传输机制。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2011083006A System and method for implementing cyclic redundancy check 有权
标题翻译：用于实施循环冗余检查的系统和方法
公开(公告)号：JP2011083006A
公开(公告)日：2011-04-21
申请号：JP2010253017
申请日：2010-11-11
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： STEELE BRIAN , WILEY GEORGE A
IPC分类号： H04L1/00
CPC分类号： H04L7/10 , G09G5/006 , G09G2370/045 , G09G2370/10 , H04L7/048
摘要： PROBLEM TO BE SOLVED: To provide systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information.
SOLUTION: There is provided a cyclic redundancy check (CRC) checker that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier. The CRC checker prepopulates the CRC generator for a unique pattern. Upon receipt of the unique pattern within a data stream received over a digital transmission link, the CRC checker proceeds to check CRCs without the need to queue and store data. In another aspect, a CRC generator system is provided that intentionally corrupts CRC values to transmit system error information. The CRC generator system includes a CRC generator 910, a CRC corrupter 920, an error detector 930 and an error value generator 940.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供用于实现循环冗余检查以改善链路初始化处理和交换系统错误信息的系统和方法。提供了包括唯一模式检测器，CRC发生器，CRC初始化器和CRC校验器的循环冗余校验（CRC）检查器。 CRC校验器预先为CRC生成器提供了一个独特的模式。在接收到通过数字传输链路接收的数据流中的唯一模式之后，CRC检查器继续检查CRC，而不需要排队和存储数据。在另一方面，提供了一种CRC发生器系统，其有意地破坏CRC值以传输系统错误信息。 CRC发生器系统包括CRC发生器910，CRC腐蚀器920，误差检测器930和误差值发生器940.版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2011041290A Method and system for updating buffer 有权
标题翻译：用于更新缓冲器的方法和系统
公开(公告)号：JP2011041290A
公开(公告)日：2011-02-24
申请号：JP2010196663
申请日：2010-09-02
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： WILEY GEORGE A , STEELE BRIAN
IPC分类号： H04L13/08
CPC分类号： G09G5/006 , G09G5/393 , H04J3/047 , H04W88/02
摘要： PROBLEM TO BE SOLVED: To provide methods and systems for updating a buffer. SOLUTION: The present invention provides a method for updating a buffer, the method including: strategically writing to the buffer to enable concurrent read and write to the buffer. The method eliminates the need for double buffering, thereby resulting in implementation cost and space savings compared to conventional buffering approaches. The method also prevents image tearing when used to update a frame buffer associated with a display, but is not limited to such applications. The present invention provides efficient mechanisms to enable buffer update across a communication link. The present invention provides a method for relaying timing information across a communication link. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供更新缓冲区的方法和系统。解决方案：本发明提供了一种用于更新缓冲器的方法，该方法包括：策略性地写入缓冲器以实现对缓冲器的并发读取和写入。该方法消除了对双缓冲的需要，从而与常规缓冲方法相比，导致实现成本和空间节省。当用于更新与显示器相关联的帧缓冲器时，该方法还防止图像撕裂，但不限于此类应用。本发明提供了有效的机制来实现通过通信链路的缓冲器更新。本发明提供一种用于在通信链路上中继定时信息的方法。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010273338A Method and system for synchronous execution of command at both ends of communication link 有权
标题翻译：用于通信链路两端同步执行命令的方法和系统
公开(公告)号：JP2010273338A
公开(公告)日：2010-12-02
申请号：JP2010108308
申请日：2010-05-10
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： KATIBIAN BEHNAM , WILEY GEORGE A
IPC分类号： H04N5/232 , H04N5/225
CPC分类号： G09G5/006 , G09G5/393 , H04J3/047 , H04W88/02
摘要： PROBLEM TO BE SOLVED: To synchronize the execution of commands transmitted by a baseband processor to a device such as a camera, through MDDI (Mobile Display Digital Interface).
SOLUTION: The method includes: generating a plurality of commands at a first module; transmitting the commands through a communication link to a second module; and associating the execution time of the commands with an independent event at the second module. When the independent event is detected, the commands are executed synchronously at the second module. The method can be specifically applied to the baseband processor in which a processor and a camera interface module 118 are connected through an MDDI link and which controls the camera through a camera module interface. An example of the baseband processor that controls the camera through a pathfinder camera module interface is described. Specific built-in mechanisms of the camera module interface that enable flexible implementation of the method are also provided.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过MDDI（移动显示数字接口）将由基带处理器发送的命令的执行同步到诸如照相机的设备。解决方案：该方法包括：在第一模块处产生多个命令; 通过通信链路将命令发送到第二模块; 以及将所述命令的执行时间与所述第二模块处的独立事件相关联。当检测到独立事件时，在第二模块上同步执行命令。该方法可以具体应用于其中处理器和摄像机接口模块118通过MDDI链路连接并且通过相机模块接口控制相机的基带处理器。描述了通过寻路器摄像机模块接口控制摄像机的基带处理器的示例。还提供了能够灵活实现该方法的相机模块接口的特定内置机制。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2010183593A High data rate interface with improved link synchronization 有权
标题翻译：具有改进的链路同步的高数据速率接口
公开(公告)号：JP2010183593A
公开(公告)日：2010-08-19
申请号：JP2010053143
申请日：2010-03-10
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： ANDERSON JON JAMES , STEELE BRIAN , WILEY GEORGE A , SHEKHAR SHASHANK
IPC分类号： H04L29/06 , G06F15/16 , H04L12/28 , H04L12/40 , H04L12/56 , H04M1/725 , H04W80/02 , H04W84/10 , H04W92/08
CPC分类号： H04L65/1069 , H04L12/40071 , H04L12/40117 , H04L29/06027 , H04L65/4069 , H04L65/80 , H04L69/18 , H04L69/22 , H04M1/72527 , H04W56/00 , Y02D70/12 , Y02D70/122 , Y02D70/144 , Y02D70/26
摘要： PROBLEM TO BE SOLVED: To transfer digital presentation data at high speed between a host device and a client device. SOLUTION: The present invention relates to a data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control data and digital presentation data. The signal protocol is used by link controllers configured to generate, transmit and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low-power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在主机设备和客户端设备之间高速传输数字呈现数据。解决方案：本发明涉及一种数据接口，用于通过链路连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成通信协议，用于传送预先选择的一组数字控制数据和数字演示数据。信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到客户端通过通信路径。该接口通过短距离“串行”类型数据链路提供了经济高效的低功耗双向高速数据传输机制。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2012227933A High data rate interface 审中-公开
标题翻译：高数据速率接口
公开(公告)号：JP2012227933A
公开(公告)日：2012-11-15
申请号：JP2012116918
申请日：2012-05-22
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： ANDERSON JON JAMES , STEELE BRIAN , WILEY GEORGE A , SHEKHAR SHASHANK
IPC分类号： H04L29/06 , H04L12/28 , H04L12/40 , H04L12/56 , H04L12/64 , H04L29/08 , H04M1/725 , H04N7/173
CPC分类号： H04L12/40052 , H04L47/283 , H04L65/608 , H04L69/03 , H04L69/10 , H04L69/18 , H04L69/323 , H04L69/324 , H04M1/72527 , Y02D70/12 , Y02D70/122 , Y02D70/144 , Y02D70/26
摘要： PROBLEM TO BE SOLVED: To provide a high data rate interface.SOLUTION: Provided is a data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control data and digital presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link.
摘要翻译：要解决的问题：提供高数据速率接口。解决方案：提供了一种数据接口，用于通过链路连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制数据和数字呈现数据的通信协议。信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并被耦合到客户端通过通信路径。该接口通过短距离“串行”类型的数据链路提供了具有成本效益，低功耗，双向，高速数据传输机制。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2011066935A High data rate interface 有权
标题翻译：高数据速率接口
公开(公告)号：JP2011066935A
公开(公告)日：2011-03-31
申请号：JP2010268227
申请日：2010-12-01
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： ANDERSON JON JAMES , STEELE BRIAN , WILEY GEORGE A , SHEKHAR SHASHANK
IPC分类号： H04L29/06 , H04L12/28 , H04L12/56 , H04M1/725
CPC分类号： H04L65/607 , H04L29/06027 , H04L69/14 , H04L69/18 , H04L69/22 , H04L69/24 , H04M1/72527 , Y02D50/30 , Y02D70/12 , Y02D70/122 , Y02D70/144 , Y02D70/26
摘要： PROBLEM TO BE SOLVED: To provide a mobile display digital interface (MDDI) that provides a cost-effective and low-power transfer mechanism enabling high-speed or very-high-speed data transfer over a short-range communication link between a host device and a client device such as display elements by using a "serial" type data link or channel. SOLUTION: The present invention relates to the data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control data and digital presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种移动显示数字接口（MDDI），其提供具有成本效益和低功率的传输机制，能够通过短距离通信链路实现高速或高速数据传输，主机设备和诸如显示元件的客户端设备，通过使用“串行”类型的数据链路或信道。解决方案：本发明涉及用于通过链路连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据的数据接口，以形成通信协议，用于传送预先选择的一组数字控制数据和数字演示数据。信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到客户端通过通信路径。该接口通过短距离“串行”类型的数据链路提供了具有成本效益，低功耗，双向，高速数据传输机制。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2011023009A High data rate interface apparatus and method 审中-公开
标题翻译：高数据速率接口设备和方法
公开(公告)号：JP2011023009A
公开(公告)日：2011-02-03
申请号：JP2010166196
申请日：2010-07-23
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： ANDERSON JON JAMES , STEELE BRIAN , WILEY GEORGE A , SHEKHAR SHASHANK
IPC分类号： G06F13/42 , G06F13/38 , H04J3/16 , H04J3/22 , H04L12/28 , H04L12/56 , H04L29/06 , H04M1/725 , H04N19/89
CPC分类号： H04L65/80 , H04L29/06027 , H04L65/1069 , H04L65/4069 , H04L69/18 , H04L69/22 , H04M1/72527 , H04N19/89 , H04N21/43615 , H04N21/4363 , Y02D70/12 , Y02D70/122 , Y02D70/144 , Y02D70/166 , Y02D70/26
摘要： PROBLEM TO BE SOLVED: To provide a new transfer mechanism for increasing the data throughput between a host device and a client display device, or between elements. SOLUTION: An apparatus is configured to generate, transmit and receive a packet which forms a communication protocol, and to form digital data in one or more types of data packets. At least one resides in the host device permanently, and a signal protocol is used by a link controller which is combined with a client through a communication path. An interface provides cost-efficient, low power, bidirectional and a high-speed data transfer mechanism on a short distance "serial" type data link and is suitable for implementation with a useful small connector and a thin flexible cable, especially, when a display element like a wearable micro display for a portable computer or a radio communication device is to be connected. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供用于增加主机设备和客户端显示设备之间或元件之间的数据吞吐量的新的传送机制。解决方案：设备被配置为生成，发送和接收形成通信协议的分组，并且在一个或多个类型的数据分组中形成数字数据。至少一个永久地驻留在主机设备中，并且由通过通信路径与客户端组合的链路控制器使用信号协议。接口在短距离“串行”型数据链路上提供了具有成本效益，低功耗，双向和高速数据传输机制，并且适用于使用有用的小连接器和薄柔性电缆的实现，特别是当显示器要像便携式计算机或无线电通信装置的可穿戴微型显示器那样连接元件。版权所有（C）2011，JPO＆INPIT

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