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1. 发明专利

JP2013078122A Method and apparatus for improving performance and user experience of mobile broadcast receiver 审中-公开
标题翻译：改善移动广播接收机性能和用户体验的方法和装置
公开(公告)号：JP2013078122A
公开(公告)日：2013-04-25
申请号：JP2012209868
申请日：2012-09-24
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： MICHAEL MATTHEW , SIVARAMAKRISHNA VEEREPALLI , SIMMAN PATEL , LI TAO
IPC分类号： H04N7/173 , G06F13/00 , H04B1/16 , H04M1/00
CPC分类号： H04N21/431 , H04H20/08 , H04H20/28 , H04H20/93 , H04H60/31 , H04H60/33 , H04H60/46 , H04H60/64 , H04H2201/30 , H04H2201/33 , H04H2201/37 , H04H2201/40 , H04N5/44543 , H04N5/44591 , H04N7/17327 , H04N21/4126 , H04N21/414 , H04N21/41407 , H04N21/436 , H04N21/4384 , H04N21/44222 , H04N21/4532 , H04N21/4858 , H04N21/6582
摘要： PROBLEM TO BE SOLVED: To provide various techniques for receiving broadcast at a mobile broadcast receiver.SOLUTION: The receiver provides user notification and automatically launches an application on the basis of user preferences. The receiver improves channel switching time by predicting future channel selection on the basis of real-time monitoring of user inputs. The receiver supports a drag-and-drop user interface. The receiver provides additional information associated with a selected broadcast stream. The receiver processes a broadcast stream and sends output data to an external device. The receiver simultaneously displays live content and stored content. The receiver simultaneously receives multiple broadcast streams to be displayed on one or more display units. The receiver collects user statistics and sends the statistics to a network entity.
摘要翻译：要解决的问题：提供用于在移动广播接收机处接收广播的各种技术。
解决方案：接收器提供用户通知，并根据用户偏好自动启动应用程序。接收机通过在用户输入的实时监控的基础上预测将来的频道选择来提高频道切换时间。接收器支持拖放式用户界面。接收机提供与所选广播流相关联的附加信息。接收机处理广播流并将输出数据发送到外部设备。接收器同时显示实况内容和存储的内容。接收机同时接收要在一个或多个显示单元上显示的多个广播流。接收方收集用户统计信息并将统计信息发送给网络实体。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2008295076A Direct converting receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：JP2008295076A
公开(公告)日：2008-12-04
申请号：JP2008177383
申请日：2008-07-07
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
IPC分类号： H03G1/00 , H04B1/16 , H03G3/20 , H03G3/30 , H04B1/30 , H04L27/22 , H04L27/38
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： PROBLEM TO BE SOLVED: To obtain a direct down converting receiver architecture having a DC loop for removing a DC offset from a signal component, a digital variable gain amplifier (DVGA) for providing a gain range, an automatic gain control (AGC) loop for performing gain control relating to the DVGA and RF/analog circuits, and a serial bus interface (SBI) unit for providing control relating to the RF/analog circuits via a serial bus. SOLUTION: The DVGA is to be effectively designed and disposed. Since these two loops mutually performs interaction, an operation mode of the VGA loop is to be selected based on an operation mode of the DC loop. Selection is made so as to be in inverse proportion to bandwidth of the DC loop in a captured mode while the DC loop is operated by the captured mode. Control is to be provided to some or all of the RF/analog circuits via the serial bus. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了获得具有用于从信号分量中去除DC偏移的DC回路的直接下变频接收机架构，用于提供增益范围的数字可变增益放大器（DVGA），自动增益控制（AGC））环路，用于执行与DVGA和RF /模拟电路相关的增益控制;以及串行总线接口（SBI）单元，用于经由串行总线提供与RF /模拟电路相关的控制。
解决方案：DVGA要有效设计和处理。由于这两个环路相互进行交互，所以基于DC循环的操作模式来选择VGA环路的操作模式。在捕捉模式下，直流环路被捕捉模式操作时，进行与直流回路的带宽成反比例的选择。将通过串行总线向部分或全部RF /模拟电路提供控制。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2010213310A Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：JP2010213310A
公开(公告)日：2010-09-24
申请号：JP2010094023
申请日：2010-04-15
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
IPC分类号： H03G1/00 , H04B1/30 , H03G3/20 , H03G3/30 , H04L27/22 , H04L27/38
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： PROBLEM TO BE SOLVED: To provide an architecture of a direct down conversion receiver capable of providing required signal gain and DC offset correction. SOLUTION: The architecture has a DC loop for removing DC offset from a signal component, a digital variable gain amplifier (DVGA) for providing a gain range, an automatic gain control (AGC) loop for performing a gain control relating to the DVGA and an RF/analog circuit, and a serial bus interface (SBI) unit for providing control to the RF/analog circuit via a serial bus. Since these two loops perform mutual interaction with each other in design and disposition of the DVGA, an operation mode of the VGA loop is selected based on an operation mode of the DC loop. Within a time period while the DC loop is operating by a capturing mode, selection is made so as to be operated in inverse proportion to a bandwidth of the DC loop in the capturing mode. The control relating to some or all of RF/analog circuits is provided via the serial bus. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够提供所需信号增益和DC偏移校正的直接下变频接收机的架构。解决方案：该架构具有用于从信号分量中去除DC偏移的直流回路，用于提供增益范围的数字可变增益放大器（DVGA），用于执行与增益范围相关的增益控制的自动增益控制（AGC） DVGA和RF /模拟电路以及串行总线接口（SBI）单元，用于通过串行总线向RF /模拟电路提供控制。由于这两个循环在DVGA的设计和配置中彼此相互作用，所以基于DC循环的操作模式来选择VGA循环的操作模式。在DC循环通过捕获模式操作的时间段内，选择在捕获模式中与DC环路的带宽成反比地运行。通过串行总线提供与RF /模拟电路中的一些或全部相关的控制。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2010193489A Direct downconversion receiver architecture 有权
标题翻译：直接导航接收机架构
公开(公告)号：JP2010193489A
公开(公告)日：2010-09-02
申请号：JP2010085217
申请日：2010-04-01
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
IPC分类号： H03G1/00 , H04B1/16 , H03G3/20 , H03G3/30 , H04L27/22 , H04L27/38
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： PROBLEM TO BE SOLVED: To provide a direct downconversion receiver architecture providing a signal gain and DC offset correction. SOLUTION: The direct downconversion receiver architecture includes: a DC loop to remove DC offset from signal components; a digital variable gain amplifier (DVGA) to provide a range of gains; an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry; and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop is selected based on the operating mode of the DC loop, since these two loops interact with each other. The duration of time the DC loop is operated in an acquisition mode is selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种提供信号增益和DC偏移校正的直接下变频接收机架构。解决方案：直接下变频接收机架构包括：DC信号消除DC偏移的DC环路; 数字可变增益放大器（DVGA）提供一系列增益; 自动增益控制（AGC）回路，为DVGA和RF /模拟电路提供增益控制; 以及串行总线接口（SBI）单元，通过串行总线提供对RF /模拟电路的控制。基于DC环路的工作模式选择VGA环路的工作模式，因为这两个环路相互交互。在采集模式下，DC环路工作的持续时间被选择为与采集模式中的DC环路带宽成反比。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009010959A Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：JP2009010959A
公开(公告)日：2009-01-15
申请号：JP2008177384
申请日：2008-07-07
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
IPC分类号： H03G1/00 , H04B1/16 , H03G3/20 , H03G3/30 , H04B1/30 , H04L27/22 , H04L27/38
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： PROBLEM TO BE SOLVED: To provide a direct downconversion receiver architecture capable of providing the required signal gain and DC offset correction. SOLUTION: A direct downconversion receiver architecture has a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够提供所需信号增益和DC偏移校正的直接下变频接收机架构。解决方案：直接下变频接收器架构具有DC环路，用于消除信号分量的DC偏移，提供一系列增益的数字可变增益放大器（DVGA），提供增益控制的自动增益控制（AGC）回路用于DVGA和RF /模拟电路，以及串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2014030226A Method and apparatus for improving performance and user experience of mobile broadcast receiver 有权
标题翻译：改善移动广播接收机性能和用户体验的方法和装置
公开(公告)号：JP2014030226A
公开(公告)日：2014-02-13
申请号：JP2013188885
申请日：2013-09-11
申请人： Qualcomm Incorporated , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： MICHAEL MATTHEW , SIVARAMAKRISHNA VEEREPALLI , SIMMAN PATEL , LI TAO
IPC分类号： H04N21/482 , H04N21/475
CPC分类号： H04N21/431 , H04H20/08 , H04H20/28 , H04H20/93 , H04H60/31 , H04H60/33 , H04H60/46 , H04H60/64 , H04H2201/30 , H04H2201/33 , H04H2201/37 , H04H2201/40 , H04N5/44543 , H04N5/44591 , H04N7/17327 , H04N21/4126 , H04N21/414 , H04N21/41407 , H04N21/436 , H04N21/4384 , H04N21/44222 , H04N21/4532 , H04N21/4858 , H04N21/6582
摘要： PROBLEM TO BE SOLVED: To provide various techniques for receiving broadcast at a mobile broadcast receiver.SOLUTION: The broadcast receiver monitors user selection of broadcast content, and determines order of user preference through that content selection operation. Based on the order of user preference, the broadcast receiver notifies the user of the presence of content among plural items of broadcast content, or automatically launches an application.
摘要翻译：要解决的问题：提供用于在移动广播接收机处接收广播的各种技术。解决方案：广播接收机监视用户对广播内容的选择，并通过该内容选择操作确定用户偏好的顺序。基于用户偏好的顺序，广播接收机通过多个广播内容的内容通知用户，或者自动地发起应用。

7. 发明专利

JP2011259451A Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：JP2011259451A
公开(公告)日：2011-12-22
申请号：JP2011149049
申请日：2011-07-05
申请人： Qualcomm Incorporated , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： LI TAO , CHRISTIAN HOLENSTEIN , INYUP KANG , BRETT C WALKER , PAUL E PETERZELL , RAGHU CHALLA , MATTHEW L SEVERSON , ARN RAGHUPATHI , GILBERT SI SHI
IPC分类号： H03G1/00 , H04B1/16 , H03G3/20 , H03G3/30 , H04B1/30 , H04L27/22 , H04L27/38
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： PROBLEM TO BE SOLVED: To provide a direct downconversion receiver that corrects signal gain and DC offset.SOLUTION: A direct downconversion receiver architecture has a DC loop to remove DC offset from signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and an RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitries are provided via the serial bus.
摘要翻译：要解决的问题：提供校正信号增益和直流偏移的直接下变频接收器。解决方案：直接下变频接收器架构具有直流回路以消除信号分量的直流偏移，提供一系列增益的数字可变增益放大器（DVGA），自动增益控制（AGC）回路，以提供增益控制 DVGA和RF /模拟电路以及通过串行总线为RF /模拟电路提供控制的串行总线接口（SBI）单元。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或所有RF /模拟电路的控制通过串行总线提供。版权所有（C）2012，JPO＆INPIT

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