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1. 发明专利

JP2011148919A Resin composition, method for producing resin composition, resin varnish, prepreg, metal-clad laminate and printed wiring board 有权
标题翻译：树脂组合物，生产树脂组合物的方法，树脂变性，PREPREG，金属层压板和印刷线路板
公开(公告)号：JP2011148919A
公开(公告)日：2011-08-04
申请号：JP2010011858
申请日：2010-01-22
申请人： Panasonic Electric Works Co Ltd , パナソニック電工株式会社
发明人： FUJIWARA HIROAKI , YAMAGUCHI MANA , SAITO HIRONORI
IPC分类号： C08L63/00 , B32B15/04 , B32B15/08 , B32B15/092 , C08G59/20 , C08J5/24 , C08L79/04 , H05K1/03
摘要： PROBLEM TO BE SOLVED: To provide a resin composition which exhibits low viscosity when converted into varnish while maintaining excellent dielectric characteristics of PPE, and of which the cured product has excellent heat resistance. SOLUTION: The resin composition containing: a reaction mixture (A) obtained by making at least a part of epoxy groups of an epoxy resin containing a triazine skeleton, having the triazine skeleton in the molecule, preliminarily react with a hydroxyl group of a low molecular weight polyphenylene ether with a number average molecular weight of 500-3,000; an epoxy resin (B) with an average molecular weight of 600 or less, having two or more epoxy groups in average in a molecule, and having a halogen concentration of less than 0.5 mass% in a molecule; a cyanate resin (C) having two or more cyanate groups in average in a molecule; and a curing accelerator (D), is used. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种在保持PPE的优异的介电特性的同时转化为清漆时显示低粘度并且其固化产物具有优异的耐热性的树脂组合物。解决方案：包含：通过在分子中制备具有三嗪骨架的含有三嗪骨架的环氧树脂的至少一部分环氧基团而获得的反应混合物（A），预先与分子中的羟基反应数均分子量为500〜3000的低分子量聚苯醚; 平均分子量为600以下的环氧树脂（B），分子中平均具有两个以上的环氧基，分子中的卤素浓度小于0.5质量％的环氧树脂（B）在分子中平均具有两个以上氰酸酯基的氰酸酯树脂（C）和固化促进剂（D）。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2011100798A Circuit board 审中-公开
标题翻译：电路板
公开(公告)号：JP2011100798A
公开(公告)日：2011-05-19
申请号：JP2009253504
申请日：2009-11-04
申请人： Panasonic Electric Works Co Ltd , パナソニック電工株式会社
发明人： TAKEDA TAKESHI , TAKASHITA HIROMITSU , FUJIWARA HIROAKI , YOSHIOKA SHINGO
IPC分类号： H05K3/10 , H05K3/22
摘要： PROBLEM TO BE SOLVED: To provide a circuit board that reduces transmission loss of an electric circuit provided in a circuit groove of an insulating layer and connected to a via. SOLUTION: The circuit board includes an insulating layer 1, and the electric circuit 2 and via 3 provided to the insulating layer 1. The circuit groove 4 and a through hole 5 communicating with the circuit groove 4 are formed in the insulating layer 1. The electric circuit 2 is provided in the circuit groove 4, and the via 3 is provided in the through hole 5. Surface roughness of an inner surface of the circuit groove 4 is less than surface roughness of an inner surface of the through hole 5. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种降低设置在绝缘层的电路槽中并连接到通孔的电路的传输损耗的电路板。解决方案：电路板包括绝缘层1和设置在绝缘层1上的电路2和通孔3.电路槽4和与电路槽4连通的通孔5形成在绝缘层中电路2设置在电路槽4中，通孔3设置在通孔5中。电路槽4的内表面的表面粗糙度小于通孔内表面的表面粗糙度 5.版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2011100797A Circuit board 有权
标题翻译：电路板
公开(公告)号：JP2011100797A
公开(公告)日：2011-05-19
申请号：JP2009253503
申请日：2009-11-04
申请人： Panasonic Electric Works Co Ltd , パナソニック電工株式会社
发明人： TAKASHITA HIROMITSU , TAKEDA TAKESHI , FUJIWARA HIROAKI , YOSHIOKA SHINGO
IPC分类号： H05K3/38 , H05K1/03 , H05K3/00 , H05K3/10 , H05K3/22 , H05K3/26
摘要： PROBLEM TO BE SOLVED: To provide a highly accurate circuit board in which base material characteristics are not lowered by a filler damage and exposure on a surface, and the adhesion of a circuit layer is improved. SOLUTION: The circuit board 10 is formed by embedding a circuit layer 13 comprising a conductor in the surface of an insulating base material 1 formed of a resin containing a filler 11. The exposed surface of the insulating base material 1 is formed without destroying the filler 11. The contact surface with the insulating base material 1 of the circuit layer 13 is formed in a rugged shape following the shape projected to the contact surface of the filler 11. Preferably, the contact surface with the insulating base material 1 of the circuit layer 13 is in contact with at least part of the filler 11 projected to the contact surface. Preferably, the filler 11 is not exposed on the exposed surface of the insulating base material 1. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种高精度的电路板，其中基材特性不会由于填料损伤和表面曝光而降低，并且电路层的粘附性得到改善。解决方案：电路板10通过在包含填料11的树脂形成的绝缘基材1的表面中埋入包括导体的电路层13而形成。绝缘基材1的暴露表面形成为没有破坏填料11.与电路层13的绝缘基材1的接触表面形成为沿着填充物11的接触表面的形状的凹凸形状。优选地，与绝缘基材1的接触面与电路层13与投影到接触表面的填料11的至少一部分接触。优选地，填料11不暴露在绝缘基材1的暴露表面上。版权所有：（C）2011，JPO＆INPIT

4. 发明专利

JP2011096947A Circuit board and manufacturing method thereof 有权
标题翻译：电路板及其制造方法
公开(公告)号：JP2011096947A
公开(公告)日：2011-05-12
申请号：JP2009251379
申请日：2009-10-30
申请人： Panasonic Electric Works Co Ltd , パナソニック電工株式会社
发明人： YOSHIOKA SHINGO , FUJIWARA HIROAKI , TAKASHITA HIROMITSU , TAKEDA TAKESHI
IPC分类号： H05K3/10 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a circuit board wherein a high-precision electric circuit is formed on an insulating substrate. SOLUTION: The circuit board includes the insulating substrate 1 which is formed by forming a resin film 2 on the outer surface of the resin film, forming a circuit trench 3 of a desired shape and depth, by forming a recess having a depth that exceeds the thickness of the resin film 2 with reference to the outer surface of the resin film 2; depositing a plating catalyst or its precursor 5 on the surface of the circuit trench 3 and the surface of the resin film 2; and then exfoliating the resin film 2, and an electroless plating film 6, which is formed on the circuit trench by performing electroless plating on the insulating substrate 1, wherein the thickness of the electroless plating film 6 is less than or equal to 0.5 of the depth of the circuit trench 3. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种在绝缘基板上形成高精度电路的电路板。解决方案：电路板包括绝缘基板1，其通过在树脂膜的外表面上形成树脂膜2而形成，通过形成具有深度的凹槽形成所需形状和深度的电路沟槽3 相对于树脂膜2的外表面超过树脂膜2的厚度; 在电路沟槽3的表面和树脂膜2的表面上沉积电镀催化剂或其前体5; 然后通过在绝缘基板1上进行化学镀而形成在电路沟槽上的化学镀膜6，其中化学镀膜6的厚度小于或等于0.5的化学镀膜6，电路沟槽深度3.版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2009081212A Method for manufacturing printed wiring board 审中-公开
标题翻译：制造印刷电路板的方法
公开(公告)号：JP2009081212A
公开(公告)日：2009-04-16
申请号：JP2007248173
申请日：2007-09-25
申请人： Panasonic Electric Works Co Ltd , パナソニック電工株式会社
发明人： FUJIWARA HIROAKI , YOSHIOKA SHINGO , WATANABE TOMOAKI , YAMAGUCHI MANA
IPC分类号： H05K3/18 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed wiring board that can manufacture the printed wiring board in which a circuit finer than a conventional one is formed with higher reliability while reducing an environmental load.
SOLUTION: In the method for manufacturing a printed wiring board, a base 3 is formed of insulating resin 1, the surface of the base 3 is coated with a resist 6, a groove 4 is formed at the base 3 to penetrate the resist 6, plating nuclei 2 are made to adhere at least to the inner surface of the groove 4, and then the resist 6 is removed. Thereafter, a circuit 5 is formed in the groove 4 by electroless plating.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造印刷电路板的方法，所述印刷线路板可以制造其中形成比常规电路更细的电路，同时降低环境负荷的可靠性更高的印刷电路板。解决方案：在制造印刷电路板的方法中，基体3由绝缘树脂1形成，基底3的表面涂覆有抗蚀剂6，在基部3处形成凹槽4以穿透抗蚀剂6，电镀核2至少粘附到凹槽4的内表面，然后去除抗蚀剂6。此后，通过无电解电镀在沟槽4中形成电路5。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2009029930A Manufacturing method for adhesive sheet with mold release film 审中-公开
标题翻译：具有模具释放膜的粘合片的制造方法
公开(公告)号：JP2009029930A
公开(公告)日：2009-02-12
申请号：JP2007195240
申请日：2007-07-26
申请人： Panasonic Electric Works Co Ltd , パナソニック電工株式会社
发明人： WATANABE TOMOAKI , YAMAGUCHI MANA , FUJIWARA HIROAKI , FUKUHARA YASUO , YOSHIOKA SHINGO
IPC分类号： C09J7/02 , B32B27/00 , B32B27/38 , B32B27/42 , C09J161/04 , C09J161/14 , C09J163/00 , H05K1/03 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for an adhesive sheet with a mold release film manufacturing the adhesive sheet with the mold release film by separating only a support film from a laminate constituted of three-layer structure comprising the support film, the adhesive sheet and the mold release film. SOLUTION: This manufacturing method for the adhesive sheet 4 with the mold release film comprises applying, onto the support film 2, an epoxy resin composition 1 containing a biphenyl type epoxy resin (A) having an average epoxy equivalent less than 450, a bisphenol A type epoxy resin (B) having 450 or more of average epoxy equivalent, and a phenol novolac resin (C) having triazine ring in a molecule, wherein a mass ratio of the bisphenol A type epoxy resin (B) to the biphenyl type epoxy resin (A) is 0.25-2. Then, the mold release film 3 is layered onto the epoxy resin composition 1, and the epoxy resin composition 1 is brought into a semi-cured state. The support film 2 is separated thereafter. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决问题的方法：提供一种具有脱模膜的粘合片的制造方法，该脱模膜通过从仅由支撑膜构成的层叠体构成的层叠体仅分离支撑膜来制造具有脱模膜的粘合片，粘合片和脱模膜。解决方案：用于具有脱模膜的粘合片4的制造方法包括将具有平均环氧当量小于450的联苯型环氧树脂（A）的环氧树脂组合物1涂覆在支撑膜2上，双酚A型环氧树脂（B）与平均环氧当量为450以上的双酚A型环氧树脂（B）和分子内具有三嗪环的苯酚酚醛清漆树脂（C），双酚A型环氧树脂（B）型环氧树脂（A）为0.25-2。然后，将脱模膜3层叠在环氧树脂组合物1上，使环氧树脂组合物1成为半固化状态。之后分离支撑膜2。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2011243790A Wiring method, structure provided wiring on surface, semiconductor device, wiring board, memory card, electric device, module, and multilayer circuit board 审中-公开
标题翻译：布线方式，结构提供的表面布线，半导体器件，接线板，存储卡，电气设备，模块和多层电路板
公开(公告)号：JP2011243790A
公开(公告)日：2011-12-01
申请号：JP2010115250
申请日：2010-05-19
申请人： Panasonic Electric Works Co Ltd , パナソニック電工株式会社
发明人： YOSHIOKA SHINGO , FUJIWARA HIROAKI , TAKASHITA HIROMITSU , TAKEDA TAKESHI , KONNO YUKO
IPC分类号： H05K3/42 , C23C18/18 , G06K19/077 , H01L23/12 , H01L25/00 , H01L25/065 , H01L25/07 , H01L25/18 , H05K1/14 , H05K3/00
CPC分类号： H05K3/184 , C23C18/1608 , C23C18/1653 , C23C18/1893 , C25D7/0607 , H01L21/4832 , H01L21/6835 , H01L23/3121 , H01L23/49541 , H01L23/49582 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2221/68377 , H01L2224/24051 , H01L2224/24137 , H01L2224/24145 , H01L2224/24146 , H01L2224/24225 , H01L2224/24226 , H01L2224/24998 , H01L2224/32145 , H01L2224/82001 , H01L2224/82039 , H01L2224/82101 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06568 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01056 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H05K1/185 , H05K3/10 , H05K3/284 , H05K3/4644 , H05K2201/10636 , H05K2201/10674 , H05K2203/0264 , H05K2203/072 , H05K2203/0723 , H05K2203/0769 , H05K2203/1407 , H05K2203/1469 , Y02P70/611 , H05K3/4661 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To increase the density of a wiring circuit.SOLUTION: A wiring method includes: forming an insulating layer 103 on a surface of a semiconductor device 1 where a plurality of connection terminals 101a, 102a are exposed, and forming a resin coating 104 on a surface of the insulating layer; forming a groove 105 having a depth equal to or larger than the thickness of the resin coating from a surface side of the resin coating to pass nearby a connection terminal to be connected, and forming continuous holes 106, 107 reaching the connection terminal to be connected from the nearby passing part; depositing a plating catalyst or a precursor thereof on surfaces of the groove and continuous holes; removing the resin coating by dissolution or swelling; and forming a plating film only at a part where the plating catalyst or the plating catalyst precursor formed of the plating catalyst remains by carrying out electroless plating, thereby providing wiring 108 having a main body portion positioned on the surface of the insulating layer and a branch portion branching off from the main body portion and extending into the insulating layer to reach the connection terminal to be connected.
摘要翻译：要解决的问题：提高布线电路的密度。解决方案：布线方法包括：在半导体器件1的暴露多个连接端子101a，102a的表面上形成绝缘层103，并在绝缘层的表面上形成树脂涂层104; 从树脂涂层的表面侧形成深度等于或大于树脂涂层的厚度的槽105，以通过要连接的连接端子，并且形成连接孔106,107到达要连接的连接端子从附近的通行部分; 在所述槽和连续孔的表面上沉积电镀催化剂或其前体; 通过溶解或溶胀去除树脂涂层; 仅在由电镀催化剂形成的电镀催化剂或电镀催化剂前体的部分进行无电解电镀而形成镀膜，由此提供具有位于绝缘层的表面上的主体部分的配线108和分支部分从主体部分分支并延伸到绝缘层中，以到达要连接的连接端子。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2011100799A Circuit board 审中-公开
标题翻译：电路板
公开(公告)号：JP2011100799A
公开(公告)日：2011-05-19
申请号：JP2009253505
申请日：2009-11-04
申请人： Panasonic Electric Works Co Ltd , パナソニック電工株式会社
发明人： TAKASHITA HIROMITSU , TAKEDA TAKESHI , FUJIWARA HIROAKI , YOSHIOKA SHINGO
IPC分类号： H05K3/10 , H05K3/18
摘要： PROBLEM TO BE SOLVED: To provide a circuit board in which a metal conductor inside a groove for circuit formation is formed by a crystal of a uniform and microfabricated grain aggregate to have a higher reliability of a circuit. SOLUTION: On the surface of an insulating base material 1, a groove 2 for circuit formation is formed. Then, the inside the groove 2 for circuit formation is filled with a metal conductor 3 formed by plating, and the circuit board is formed. The crystal grain aggregate of the metal conductor has an average diameter length ≤10 μm, and the metal conductor 3 is formed of the crystal of the uniform and microfabricated grain aggregate. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种电路板，其中用于电路形成的沟槽内的金属导体由均匀且微细的颗粒聚集体的晶体形成，以具有更高的电路可靠性。解决方案：在绝缘基材1的表面上形成用于电路形成的槽2。然后，用于电路形成的槽2的内部填充有通过电镀形成的金属导体3，并且形成电路板。金属导体的晶粒聚集体的平均直径长度≤10μm，金属导体3由均匀的微细骨料的晶体形成。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2011100795A Circuit board 有权
标题翻译：电路板
公开(公告)号：JP2011100795A
公开(公告)日：2011-05-19
申请号：JP2009253501
申请日：2009-11-04
申请人： Panasonic Electric Works Co Ltd , パナソニック電工株式会社
发明人： YOSHIOKA SHINGO , FUJIWARA HIROAKI , TAKASHITA HIROMITSU , TAKEDA TAKESHI
IPC分类号： H05K1/02 , H05K3/10
摘要： PROBLEM TO BE SOLVED: To provide a circuit board making it harder to peel a pad part with a large area than that of a line part from an insulating substrate, and enabling stable mounting of surface mount parts non-tiltedly. SOLUTION: The circuit board 10 is formed by burying a line part 9 and a pad part 8 as an electrical circuit in an insulating substrate 1 to be exposed. A circuit groove 3 having the line part 9 formed therein is formed shallow, and a circuit groove 3 having the pad part 8 formed therein is formed deep. The thickness of the pad part 8 is approximately uniform. COPYRIGHT: (C)2011,JPO&INPIT

10. 发明专利

JP2011049294A Manufacturing method of circuit board and circuit board obtained thereby 有权
标题翻译：电路板和电路板的制造方法
公开(公告)号：JP2011049294A
公开(公告)日：2011-03-10
申请号：JP2009195515
申请日：2009-08-26
申请人： Panasonic Electric Works Co Ltd , パナソニック電工株式会社
发明人： TAKASHITA HIROMITSU , TAKEDA TAKESHI , FUJIWARA HIROAKI , YOSHIOKA SHINGO
IPC分类号： H05K3/10 , H05K3/02 , H05K3/18 , H05K3/22 , H05K3/42
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit board, which forms the circuit board with high precision on an insulation base material, even for an electrical circuit having a narrow line width and a line interval.
SOLUTION: The manufacturing method of a circuit board includes: a film formation process to form a resin film 2 in the surface of the insulation base material 1; a circuit pattern formation process to form a circuit pattern portion of a circuit groove 3 of a predetermined shape and depth by applying laser processing or machine processing to the insulation base material 1 from the outside surface of the resin film 2; a catalyst adhesion process to adhere a plating catalyst or its precursor 5 to the surface of the circuit pattern portion and the surface of the resin film 2; a film peeling process to peel off the resin film 2 from the insulation base material 1; and a plating processing process to apply electroless plating to the insulation base material 1 of which the resin film 2 is peeled off. The film formation process uses, as the insulation base material 1, a material which has a smooth surface having a 0.5 μm or less surface roughness (Ra), and the resin film 2 is formed on the smooth surface side.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使对于具有窄线宽和线间隔的电路，提供一种在绝缘基材上高精度地形成电路板的电路板的制造方法。解决方案：电路板的制造方法包括：在绝缘基材1的表面形成树脂膜2的成膜工艺; 通过从树脂膜2的外表面向绝缘基材1施加激光加工或机械加工，形成具有预定形状和深度的电路槽3的电路图形部分的电路图形形成处理; 将电镀催化剂或其前体5粘附到电路图案部分和树脂膜2的表面的催化剂粘合方法; 从绝缘基材1剥离树脂膜2的膜剥离处理; 以及对剥离树脂膜2的绝缘基材1施加化学镀的电镀处理工序。成膜方法使用具有0.5μm以下表面粗糙度（Ra）的光滑表面的材料作为绝缘基材1，并且树脂膜2形成在光滑表面侧。版权所有（C）2011，JPO＆INPIT

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