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1. 发明专利

JP2007180595A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007180595A
公开(公告)日：2007-07-12
申请号：JP2007093318
申请日：2007-03-30
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： SAEKI YOSHIHIRO
IPC分类号： H01L21/60
CPC分类号： H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/49 , H01L2224/49171 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To readily and accurately carry out changes in the arrangement of bonding pads. SOLUTION: A semiconductor chip 40 having a plurality of bonding pads 41 is fixed firmly on a die pad 31. A relay chip 50, having a size smaller than the semiconductor chip 40, is fixed firmly on the semiconductor chip 40. The relay chip 50 has a plurality of bonding pads 51, and the bonding pads 51 are connected to each other via wiring patterns 52, to change the arrangement of the bonding pads 41 on the semiconductor chip 40 side to a different direction. The bonding pads 41 are connected to the bonding pads 51 with wires 61, and the bonding pads 51 are connected to bonding pads 33 on a lead frame 30 side with wires 62. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了容易且准确地执行焊盘排列的改变。解决方案：具有多个接合焊盘41的半导体芯片40牢固地固定在芯片焊盘31上。具有小于半导体芯片40的尺寸的中继芯片50牢固地固定在半导体芯片40上。继电器芯片50具有多个接合焊盘51，并且接合焊盘51经由布线图案52彼此连接，以将半导体芯片40侧的接合焊盘41的布置改变为不同的方向。接合焊盘41用导线61连接到接合焊盘51，并且接合焊盘51通过导线62连接到引线框架30侧的焊盘33.版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007180594A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007180594A
公开(公告)日：2007-07-12
申请号：JP2007093317
申请日：2007-03-30
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： SAEKI YOSHIHIRO
IPC分类号： H01L21/60
CPC分类号： H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2924/01019 , H01L2924/01079 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To simply and accurately execute change in the arrangement of bonding pads.
SOLUTION: A semiconductor chip 40, having a plurality of bonding pads 41, is firmly fixed on a die pad 31. A relay chip 50 is firmly fixed on the semiconductor chip 40. The relay chip 50 has a plurality of bonding pads 51, and the bonding pads 51 are connected with one another via a wiring pattern 52 of a multilayer wiring structure, to change the arrangement of the bonding pads 41 on the semiconductor chip 40 side to a different direction. The bonding pads 41 are connected to the bonding pads 51 with wires 61, and the bonding pads 51 are connected to bonding pads 33 on a lead frame 30 side via wires 62.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：简单而准确地执行焊盘排列的改变。解决方案：具有多个接合焊盘41的半导体芯片40牢固地固定在芯片焊盘31上。中继芯片50牢固地固定在半导体芯片40上。中继芯片50具有多个焊盘 51和接合焊盘51经由多层布线结构的布线图案52彼此连接，以将半导体芯片40侧的接合焊盘41的布置改变到不同的方向。接合焊盘41通过导线61连接到接合焊盘51，并且焊盘51通过导线62连接到引线框架30侧上的接合焊盘33.（C）2007，JPO＆INPIT

3. 发明专利

JP2006108588A Manufacturing method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006108588A
公开(公告)日：2006-04-20
申请号：JP2004296731
申请日：2004-10-08
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： SAEKI YOSHIHIRO
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L25/0657 , H01L21/563 , H01L24/28 , H01L2224/73203 , H01L2224/83102 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/01006 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082
摘要： PROBLEM TO BE SOLVED: To provide a means by which to uniformly implant an underfill agent into clearances between semiconductor devices, formed by stacking a plurality of semiconductor devices as well as preventing an interface from being formed between layers of the underfill agent, after having been cured.
SOLUTION: The manufacturing method for a semiconductor device, which is formed by stacking a plurality of semiconductor devices on a substrate, includes the steps of forming a plurality of stages by stacking the plurality of semiconductor devices on the substrate; setting the substrates to be approximately perpendicular and filling an underfill agent into the clearances between the substrates and the semiconductor devices, and the clearances between the stacked semiconductor devices from the top of the side face of the stacked semiconductor devices by using a nozzle; and curing the filled underfill agent.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种将底部填充剂均匀地注入到通过堆叠多个半导体器件形成的半导体器件之间的间隙以及防止在底层填充剂的层之间形成界面的手段，治愈后。解决方案：通过在基板上层叠多个半导体器件而形成的半导体器件的制造方法包括以下步骤：通过在基板上堆叠多个半导体器件来形成多个级; 将基板大致垂直设置，并将底部填充剂填充到基板和半导体器件之间的间隙中，以及通过使用喷嘴从层叠的半导体器件的侧面的顶部开始堆叠的半导体器件之间的间隙; 并固化填充的填充剂。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005136299A Semiconductor chip and semiconductor device 有权
标题翻译：半导体芯片和半导体器件
公开(公告)号：JP2005136299A
公开(公告)日：2005-05-26
申请号：JP2003372265
申请日：2003-10-31
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： SAEKI YOSHIHIRO
IPC分类号： H01L25/18 , H01L21/60 , H01L23/485 , H01L23/498 , H01L23/538 , H01L25/065 , H01L25/07
CPC分类号： H01L24/06 , H01L23/49833 , H01L23/5385 , H01L24/02 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48235 , H01L2224/48464 , H01L2224/48599 , H01L2224/4911 , H01L2224/49175 , H01L2224/4943 , H01L2224/73265 , H01L2224/85399 , H01L2225/06506 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To prevent short-circuiting by the contact of bonding wires, and to miniaturize a semiconductor device. SOLUTION: A semiconductor chip 100, in which a main surface 110a is formed in a square, comprises a first side for composing the main surface; a second side 111b that opposes the first side 111a; a group of main electrode pads 112X comprising a plurality of main electrode pads 112 arranged on the main surface along the first side; a first group of electrode pads 114X comprising a plurality of first electrode pads 114 arranged between the first side and a group of main electrode pads; a group of second electrode pads 116X comprising a plurality of second electrode pads 116 arranged on the main surface along the second side; a wiring 132 between first pads for connecting a main electrode pad and a first electrode pad; and a wiring 134 between second pads for connecting the main electrode pad and a second electrode pad. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止接合线的接触短路，并且使半导体器件小型化。解决方案：主表面110a形成为正方形的半导体芯片100包括用于构成主表面的第一侧; 与第一侧111a相对的第二侧111b; 一组主电极焊盘112X，包括沿着第一侧布置在主表面上的多个主电极焊盘112; 包括布置在第一侧和一组主电极焊盘之间的多个第一电极焊盘114的第一组电极焊盘114X; 一组第二电极焊盘116X，包括沿第二侧布置在主表面上的多个第二电极焊盘116; 用于连接主电极焊盘和第一电极焊盘的第一焊盘之间的布线132; 以及用于连接主电极焊盘和第二电极焊盘的第二焊盘之间的布线134。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2008252026A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008252026A
公开(公告)日：2008-10-16
申请号：JP2007094715
申请日：2007-03-30
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： SAEKI YOSHIHIRO
IPC分类号： H01L23/28 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/3157 , H01L25/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/26175 , H01L2225/06513 , H01L2225/06517 , H01L2924/00014 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing an effluence of a liquid resin and reducing the size of a substrate. SOLUTION: The semiconductor device includes a chip 12 rectangular in plan view provided on a mounting region on a substrate 10, a liquid resin layer 15 provided on the lower portion and side surface of the chip 12, and a plurality of dams 16 formed on the substrate 10 so as to be along the side surface of the chip 12. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够防止液体树脂流出并减小基板尺寸的半导体器件。解决方案：半导体器件包括设置在基板10上的安装区域上的平面图中矩形的矩形12，设置在芯片12的下部和侧表面上的液体树脂层15和多个堤坝16 形成在基板10上以沿着芯片12的侧表面。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008252027A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008252027A
公开(公告)日：2008-10-16
申请号：JP2007094716
申请日：2007-03-30
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： SAEKI YOSHIHIRO
IPC分类号： H01L23/28
CPC分类号： H01L21/563 , H01L24/28 , H01L24/32 , H01L24/48 , H01L24/81 , H01L24/85 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/26145 , H01L2224/26175 , H01L2224/27013 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/81801 , H01L2224/83051 , H01L2224/83102 , H01L2224/83365 , H01L2224/85 , H01L2224/92125 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To protect a wiring on a surface of a chip by preventing effluence of a liquid resin.
SOLUTION: A semiconductor device includes a first chip 10 rectangular in plan view having a wiring, electrode pads 14 and a chip mounting region; first dams 16 provided around the electrode pads 14 and the chip mounting region on the chip 10 and having the covered wiring; a second chip 12 rectangular in plan view flip-chip mounted on the chip mounting region; and an underfill 18 formed by filling the liquid resin between the first chip 10 rectangular in plan view.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过防止液体树脂的流出来保护芯片表面上的布线。解决方案：半导体器件包括具有布线的平面图矩形的第一芯片10，电极焊盘14和芯片安装区域; 设置在电极焊盘14周围的第一堤坝16和芯片10上的芯片安装区域，并具有覆盖的布线; 安装在芯片安装区域上的平面图倒装芯片的矩形矩形的第二芯片12; 以及通过在平面图中将第一芯片10矩形填充之间的液体树脂形成的底部填充物18。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2007095747A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007095747A
公开(公告)日：2007-04-12
申请号：JP2005279524
申请日：2005-09-27
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： SAEKI YOSHIHIRO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L21/561 , H01L23/3128 , H01L24/97 , H01L25/50 , H01L2224/16 , H01L2224/97 , H01L2225/06513 , H01L2225/06586 , H01L2924/01006 , H01L2924/01033 , H01L2924/01074 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2224/81 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor devices capable of obtaining a larger number of semiconductor devices than before, even when using the same lamination process as before. SOLUTION: A structure 100 is formed, comprising a substrate 9, and at least one chip 12 laminated on the substrate 9. The structure 100 is divided into a plurality of divided structures 110, 120, 130, 140. Respective divided structures 110, 120, 130, 140 constitute a single semiconductor device. A laminated structure 100, formed by using available lamination method, is divided into the plurality of divided structures 110, 120, 130, 140 by using the available method, thus increasing the number of obtainable semiconductor devices by the number of divided structures. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使使用与之前相同的层压工艺，也提供了一种能够获得比以前更多数量的半导体器件的半导体器件的制造方法。解决方案：形成包括基板9和层叠在基板9上的至少一个芯片12的结构100.结构100被分成多个分割结构110,120,130,140。分开的结构 110,120,130,140构成单个半导体器件。通过使用可用层叠方法形成的层叠结构100通过使用可用的方法被分成多个分割结构110,120,130,140，从而通过分割结构的数量增加可获得的半导体器件的数量。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2007095780A Tool and method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的工具和方法
公开(公告)号：JP2007095780A
公开(公告)日：2007-04-12
申请号：JP2005279968
申请日：2005-09-27
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： SAEKI YOSHIHIRO
IPC分类号： H01L21/301
CPC分类号： H01L21/6838
摘要： PROBLEM TO BE SOLVED: To provide a tool for manufacturing a semiconductor device that enables stable dicing and easy pickup. SOLUTION: The tool can form closed cavities C at a portion to a semiconductor wafer mounted on the upper section by a lattice section 11 and a bottom section 13 for supporting a cut-off region for dividing the semiconductor wafer into semiconductor chips. A plurality of cavities C are connected by a connecting hole 11a provided at the lattice section 11 and takes in and out inner air by an air supply and exhaust port 12a provided at an enclosure section 12, thus storing irregularities in the cavities C, even if there are the irregularities, such a bump, on the back of the semiconductor wafer, and hence fixing the semiconductor wafer to the tool reliably. The cut semiconductor chip can be taken out easily, by opening the air supply and exhaust port 12a to return the inside of the cavity to normal pressure. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于制造半导体器件的工具，其能够进行稳定的切割和容易拾取。解决方案：工具可以通过晶格部分11和用于支撑用于将半导体晶片分成半导体芯片的截止区域的底部13在安装在上部的半导体晶片的一部分处形成闭合腔C. 多个空腔C通过设置在网格部分11处的连接孔11a连接，并且通过设置在封闭部分12处的空气供给和排出端口12a来进出内部空气，从而在空腔C中存储不规则性，即使在半导体晶片的背面存在不规则的凹凸，因此可靠地将半导体晶片固定到工具上。可以通过打开供气和排气口12a来将空腔内部返回到正常压力，从而容易地取出切割的半导体芯片。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2007066932A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007066932A
公开(公告)日：2007-03-15
申请号：JP2005247068
申请日：2005-08-29
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： SAEKI YOSHIHIRO
IPC分类号： H01L23/28
CPC分类号： H01L23/49833 , H01L21/561 , H01L23/3128 , H01L23/49816 , H01L23/562 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/73253 , H01L2224/8121 , H01L2224/81815 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06582 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/15311 , H01L2924/181 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a means to reduce the warpage of a semiconductor device when a thermal expansion coefficient of a wiring board differs from that of a sealing resin layer. SOLUTION: The semiconductor device is provided with a lower substrate having a wiring pattern which is formed by a plurality of wirings, a semiconductor chip which is located above he lower substrate and is electrically connected with the wirings, an intermediate member to seal the semiconductor chip substantially and in columnar manner, and a resin plate to substantially cover the entire upper surface of the intermediate member. The thermal expansion coefficient of the resin plate is made almost the same as that of the lower substrate. COPYRIGHT: (C)2007,JPO&INPIT

10. 发明专利

JP2006269861A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006269861A
公开(公告)日：2006-10-05
申请号：JP2005087644
申请日：2005-03-25
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： SAEKI YOSHIHIRO
IPC分类号： H01L23/29 , H01L21/56 , H01L23/31 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2225/06513 , H01L2225/06555 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： PROBLEM TO BE SOLVED: To provide a means for reducing the warp of a semiconductor device which uses a lower substrate having a thermal expansion coefficient different from its lower seal resin layer. SOLUTION: The semiconductor device 1 comprises a silicon substrate 2 having a wiring pattern formed by a plurality of wirings, a semiconductor chip 6 located above the silicon substrate 2 which is electrically connected to the wirings, a seal resin layer 9 substantially sealing the semiconductor chip 6 like a column, and a metal plate 10 substantially covering the entire upside of the seal resin layer 9. The metal plate 10 and the silicon substrate 2 have approximately the same thermal expansion coefficient. COPYRIGHT: (C)2007,JPO&INPIT

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