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1. 发明专利

JPH0757459A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0757459A
公开(公告)日：1995-03-03
申请号：JP19840493
申请日：1993-08-10
申请人： OKI MICRO DESIGN MIYAZAKI KK , OKI ELECTRIC IND CO LTD
发明人： KAI YASUHIRO , ASHIZAWA YUICHI
IPC分类号： G11C11/41 , G11C11/401 , G11C11/408
摘要： PURPOSE:To make it possible to have high speed serial access by one counter without using a clock signal by generating an address with the counter addition operating a bisected memory array with the least significant address pulse. CONSTITUTION:At the time of the serial access, an external input from terminals other than the least significant address terminal AO is inhibited, and address switching circuits 24, 25 and output latch circuits 17a, 17b, etc., are controlled by the least significant address pulse from the terminal AO, and the bisected memory arrays 10a, 10b are selected alternately. Simultaneously, the counter 22 is counted up according to the least significant address pulse, and the address is generated, and the arrays 10a, 10b are serial accessed alternately, and the read data are outputted through an output switching circuit 27. By such a constitution, a semiconductor memory capable of having high speed serial access by one counter without using a control circuit activated in response to the clock signal is obtained.

2. 发明专利

JPH10283792A NONVOLATILE MEMORY 失效
公开(公告)号：JPH10283792A
公开(公告)日：1998-10-23
申请号：JP20654594
申请日：1994-08-31
申请人： OKI MICRO DESIGN MIYAZAKI KK , OKI ELECTRIC IND CO LTD
发明人： KAI YASUHIRO , KOKUBU HITOSHI
IPC分类号： G11C17/00 , G11C8/08 , G11C17/18 , G11C16/06
摘要： PURPOSE: To prevent the occurrence of leakage from a large-capacity mask at chip standby time. CONSTITUTION: Of a plurality of address buffers, a specific buffer is provided with a NAND gate 15 which finds logic based on the level of a signal CE. The NAND gate 15 fixes the logic levels of the output addresses AN and AN/ of the specific address buffer. Consequently, the level of a control signal B* obtained through a pre-decoder becomes 'L' and the logic level of the output of an inverter 21 is fixed at 'H'. Therefore, the logic level between the drain and source of an NMOS 23 becomes constant and the occurrence of leakage is prevented at chip standby time regardless of the level of a control signal C inputted to the gates of a PMOS 22 and the NMOS 23.

3. 发明专利

JPH1153892A READ-ONLY MEMORY 失效
公开(公告)号：JPH1153892A
公开(公告)日：1999-02-26
申请号：JP21038197
申请日：1997-08-05
申请人： OKI MICRO DESIGN MIYAZAKI KK , OKI ELECTRIC IND CO LTD
发明人： KAI YASUHIRO , NAGATOMO MASAHIKO
IPC分类号： G11C16/06 , G11C17/00 , G11C17/12
摘要： PROBLEM TO BE SOLVED: To provide a mask ROM and the like capable of realizing an accurate readout. SOLUTION: One of bit lines BL0-BLn is selected by a multiplexer 12 to output a readout current to a current detecting section 14a via a resistor 13. The readout current is 0 or has a variable value larger than the minimum current I in accordance with stored contents at a plurality of MOS 11i ,j which are other than the MOS 11i ,j selected by a word line WLi but located on the same bit line as the selected one. A DMOS 150 and a plurality of EMOS 151 -157 connected in series are provided on a dummy bit line DBL which is provided adjacent to and in parallel with a bit line BLn. Gates of the DMOS 150 and the plurality of EMOS 151 -157 are respectively connected to and fixed at 'L' and 'H', and the dummy bit line DBL is connected to the current detecting section 14a via a resistor 16 having a resistance value of 2R. Thus, the dummy bit line DBL is always supplied with 1/2 of the minimum current I at the bit lines BLO-BLn, resulting in an accurate readout.

4. 发明专利

JPH1165936A MEMORY DEVICE 失效
公开(公告)号：JPH1165936A
公开(公告)日：1999-03-09
申请号：JP11368998
申请日：1998-04-23
申请人： OKI MICRO DESIGN MIYAZAKI KK , OKI ELECTRIC IND CO LTD
发明人： KAI YASUHIRO
IPC分类号： G06F12/14 , G06F21/24 , G11C7/24 , G11C16/22
摘要： PROBLEM TO BE SOLVED: To provide a memory device which can control read. SOLUTION: When a SEC (identification information) signal is 'H', a read control means compares addresses AN1 iN and AN 2iN with a preset value and when they are coincident, a CSB (control signal) is turned to 'H' but when they are not coincident, the CSB is turned to 'L'. When the CSB is 'H', a sense amplifier 6 reads data out of a memory cell array 1 selected by an X decoder 3 and a Y decoder 5 and a buffer 7 outputs the read data to the outside. When the CSB is 'L', the sense amplifier 6 and the buffer 7 are not operated.

5. 发明专利

JPH06103789A NON-VOLATILE MEMORY SYSTEM 失效
公开(公告)号：JPH06103789A
公开(公告)日：1994-04-15
申请号：JP24968592
申请日：1992-09-18
申请人： OKI MICRO DESIGN MIYAZAKI KK , OKI ELECTRIC IND CO LTD
发明人： KAI YASUHIRO
IPC分类号： G11C17/00 , G11C16/06 , H01L21/8246 , H01L27/112
摘要： PURPOSE:To eliminate delay of operation and malfunction of a sense amplifier in circuit constitution of a non-volatile memory (embodiment:mask ROM). CONSTITUTION:A dummy cell 5 is provided in a sense amplifier 4 between memory arrays 1a and 1b which are divided, while transistors Tr1 and Tr3 which gates an address signal A selecting memory arrays 1a and 1b and a inverted signal far A are provided besides transistors Tr2 and Tr4. When a capacity value of a bit line 2a or 2b is selected by a pair of memory array 1a or 1b, all other memory array 1b or 1a are made dummies.

6. 发明专利

JP2009026425A Sense amplifier 审中-公开
标题翻译：感应放大器
公开(公告)号：JP2009026425A
公开(公告)日：2009-02-05
申请号：JP2007191133
申请日：2007-07-23
申请人： Oki Electric Ind Co Ltd , Oki Micro Design Co Ltd , 株式会社沖マイクロデザイン , 沖電気工業株式会社
发明人： KAI YASUHIRO
IPC分类号： G11C16/06 , G11C11/419
摘要： PROBLEM TO BE SOLVED: To reduce the access time of a sense amplifier by suppressing the output of dummy data when shifting from a standby state to an active state. SOLUTION: The sense amplifier including: a current detection part 40 made inactive during standby and, active during normal operation, and generating a reference voltage REF on the basis of a current output from a reference memory array 20; a current detection part 30 generating a detection voltage DTO on the basis of a current output from a memory array 10 to be read and the reference voltage REF; and a differential amplification part 50 amplifying the voltage of the difference between the reference voltage REF and the detection voltage DTO to output readout RD. A current detection part 70 is provided, which generates a voltage DTA according to the current output from the memory cell array 10 for a fixed time when shifting from standby to a normal operation and provides it to the differential amplification part 50 as the detection voltage DT. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过在从待机状态转换到活动状态时抑制虚拟数据的输出来减小读出放大器的访问时间。解决方案：读出放大器包括：在待机期间使电流检测部分40无效并且在正常操作期间有效，并且基于从参考存储器阵列20输出的电流产生参考电压REF; 电流检测部分30基于从要读取的存储器阵列10输出的电流和参考电压REF产生检测电压DTO; 以及差分放大部分50，放大参考电压REF和检测电压DTO之差的电压，以输出读出RD。提供电流检测部分70，当从待机状态转换到正常操作时，产生根据从存储单元阵列10输出的电流一定时间的电压DTA，并将其提供给差分放大部分50作为检测电压DT 。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2007234150A Sense amplifier 审中-公开
标题翻译：感应放大器
公开(公告)号：JP2007234150A
公开(公告)日：2007-09-13
申请号：JP2006055984
申请日：2006-03-02
申请人： Oki Electric Ind Co Ltd , Oki Micro Design Co Ltd , 株式会社沖マイクロデザイン , 沖電気工業株式会社
发明人： KAI YASUHIRO
IPC分类号： G11C16/06
CPC分类号： G11C7/062 , G11C7/067 , G11C7/14 , G11C7/20 , G11C16/28 , G11C2207/063 , G11C2207/2227
摘要： PROBLEM TO BE SOLVED: To shorten a shift time from a standby state of a current detection type sense amplifier to an operating state. SOLUTION: In the sense amplifier provided with a current sense circuit 10 outputting detected voltage DTO corresponding to a current to be compared, a current sense circuit 20 outputting reference voltage VREF corresponding to the reference current, and a comparison circuit 30 comparing the detected voltage DTO with the reference voltage VREF and outputting the compared result, the current sense circuit 20 is operated according to a chip control signal CEB, the current sense circuit 10 is operated by a delay chip control signal DCEB in which the chip control signal CEB is delayed by the prescribed time by a delay circuit 40. Thereby, in the point of time at which operation of the current sense circuit 10 is started, since the current sense circuit 20 outputs the prescribed reference voltage VREF, detected voltage DTO is converged to the prescribed level quickly without performing feedback operation in which rapid rise and fall are repeated. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：缩短从当前检测型读出放大器的待机状态到操作状态的移位时间。解决方案：在设置有输出与要比较的电流相对应的检测电压DTO的电流检测电路10的读出放大器中，输出与参考电流相对应的参考电压VREF的电流检测电路20和比较电路检测电压DTO与参考电压VREF并输出比较结果，电流检测电路20根据芯片控制信号CEB工作，电流检测电路10由延迟芯片控制信号DCEB操作，其中芯片控制信号CEB 由延迟电路40延迟规定的时间。由此，在电流检测电路10的动作开始的时刻，由于电流检测电路20输出规定的基准电压VREF，所以检测电压DTO收敛到在不执行重复快速上升和下降的反馈操作的情况下快速地进行规定的水平。版权所有（C）2007，JPO＆INPIT

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