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1. 发明专利

JPS57101929A COMMON MEMORY ACCESS SYSTEM FROM DATA CHANNEL DEVICE 失效
公开(公告)号：JPS57101929A
公开(公告)日：1982-06-24
申请号：JP17848780
申请日：1980-12-17
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： OKAYASU MASAHARU , SAITOU ISAO , TAKAHASHI TOSHIHIRO , YAZAWA KATSUHIKO , IWAMOTO YOSHIHARU , ISHIKAWA TAKAHARU
IPC分类号： G06F15/16 , G06F12/00 , G06F13/12 , G06F13/16 , G06F15/167
摘要： PURPOSE:To execute the access easily, by executing the common memory access from a data channel device, through a common memory connection control part of a processor which has sent out an operation command to the data channel device. CONSTITUTION:Double common memories 1a, 1b are used in common by each processor 2a-2n. A data channel device 6 has a memory request controlling part 60, a processor number storage part 61, and a processor selecting part 62. In this state, a memory request from the device 6 is generated in the controlling part 60, and in accordance with display of the storage part 61, for instance, a memory 3a is selected by the selection part 62, and is transferred to a contention selection part 21 of the processor. The memory request of the device 6, which has been selected by this selection part 21 is transferred to a connection controlling part 23 by a memory switching part 22. Subsequently, the controlling part 23 receives the control information for connecting the devices 2a-2n and buses 7a, 7b, from a system controlling part 24, and sends out an access signal to the common memories 1a, 1b.

2. 发明专利

JPS58151625A INPUT/OUTPUT APPARATUS CONTROLLING SYSTEM 失效
公开(公告)号：JPS58151625A
公开(公告)日：1983-09-08
申请号：JP3226182
申请日：1982-03-03
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： FUJII SATORU , SUMIDA MITSUO , MINAMIZAWA MUTSUO , ITOU TOSHINORI , MASUDA TAKESHI , ISHIKAWA TAKAHARU
IPC分类号： G06F13/12 , G06F13/20 , G06F13/366
摘要： PURPOSE:To control many input/output apparatuses by small number of input/ output apparatus controlling circuits, by providing a connecting circuit for connecting the input/output apparatus controlling circuit and one optional set of plural input/output apparatuses, and a connection controlling circuit for controlling said circuit. CONSTITUTION:In an input/output apparatus controlling system for executing the transmision and reception of information between an input/output controlling circuit 1 and plural input/output apparatuses 2-1-2-n, through an input/output apparatus controlling circuit, a connecting circuit 4 is provided between small number of input/output apparatus controlling circuits 3-1-3-3 and many apparatuses 2-1-2-n. Also, between the circuit 4 and the circuit 1, a connection controlling circuit 5 for controlling the connection of the cicuit 4 is provided. The circuit 5 monitors a connection request from the apparatuses 2-1-2-n, and controls the circuit 4 so that unconnected circuits 3-1-3-3 are connected to the input/output apparatus which generates the connection request. In this way, many input/output apparatuses are connected efficently with a small number of input/output apparatus controlling circuits, of which an economical input/output control device can be constituted.

3. 发明专利

JPS57125454A System for processing of multiprocessor 失效
标题翻译：多处理器处理系统
公开(公告)号：JPS57125454A
公开(公告)日：1982-08-04
申请号：JP1074081
申请日：1981-01-29
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： OKA HIROSHI , MASUO KAZUYUKI , DAIDOUJI YUTAKA , DEWA HIROSHI , ISHIKAWA TAKAHARU
IPC分类号： G06F11/00 , G06F9/52 , G06F12/00 , G06F13/00 , G06F15/16 , G06F15/177
摘要： PURPOSE: To protect contents of a specific area of a common storage device, which is used by one processor by using a test and set flag for the request address of the common storage device and to make it possible that another processor writes data into this area when the processor is faulty.
CONSTITUTION: A test and set instruction is sent from plural processors 20W22 to a common storage controlling device 30 through a common bus 40 and is accepted by an order acceptance controlling circuit 60 of the device 30, and an address sent from common storage devices 10W12 is held in an address register 61. Data to be written in an address corresponding to contents of the register 61 is held in a data register 62, and a test and set flag from processors 20W22 is set to a test and set controlling circuit 63. Thus, contents of a specific area of devices 10W12 which is used by one of processors 20W22, and the fault of this processor is discriminated by the circuit 63 to permit another processor to write data into this area.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：为了保护一个处理器使用的公共存储设备的特定区域的内容，通过使用公共存储设备的请求地址的测试和设置标志，并使另一个处理器可以将数据写入该区域处理器故障时。构成：通过公共总线40将测试和设定指令从多个处理器20-22发送到公共存储控制装置30，并被设备30的订单接受控制电路60接受，并且从公共存储设备 10-12被保存在地址寄存器61中。要写入与寄存器61的内容相对应的地址的数据被保存在数据寄存器62中，并且来自处理器20-22的测试和设置标志被设置为测试，因此，由处理器20-22中的一个使用的设备10-12的特定区域的内容和该处理器的故障被电路63区分，以允许另一处理器将数据写入该区域。

4. 发明专利

JPS5783837A Information processor 失效
标题翻译：信息处理器
公开(公告)号：JPS5783837A
公开(公告)日：1982-05-25
申请号：JP15827280
申请日：1980-11-12
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： IKUTA AKIRA , SUYAMA MASATO , KAJIZUKA SHIYOUJI , OKA HIROSHI , ISHIKAWA TAKAHARU
IPC分类号： G06F13/14 , G06F9/46 , G06F13/36 , G06F13/37
CPC分类号： G06F13/36
摘要： PURPOSE:To transmit signals to a control circuit surely, by requesting the access through signal lines of two systems in the information processoring device where access request signals of plural processors are cascaded. CONSTITUTION:Request signals are generated from respective request generating circuits 2-1-2-n of n-number processor 1-1-1-n and are sent to a control circuit 8 from request circuits 3-1-3-n and 4-1-4-n through common signal lines 5-7 and 10-15. When the request signal exists on either of signal lines 7 and 15, a receiving circuit 9 is operated. Consequently, even if any processor, for example, the processor 1-2 becomes faulty and the power source is turned off, signals are transmitted surely to control circuits 3-1 and 4-3-4-n of other processors 1-1 and 1-3-1-n.
摘要翻译：目的：通过请求通过信号处理设备中的两个系统的信号线进行信号传输到控制电路，其中级联多个处理器的访问请求信号。构成：从n号处理器1-1-1-n的各个请求发生电路2-1-2-n生成请求信号，并从请求电路3-1-3-n和4发送到控制电路8 -1-4-n通过公共信号线5-7和10-15。当请求信号存在于信号线7和15中的任何一个时，接收电路9被操作。因此，即使处理器（例如处理器1-2）变得有故障并且电源被断开，也可以将信号可靠地发送到其他处理器1-1和...的控制电路3-1和4-3-4-n， 1-3-1-n。

5. 发明专利

JPH0216659A TRANSACTION TRACING SYSTEM 失效
公开(公告)号：JPH0216659A
公开(公告)日：1990-01-19
申请号：JP16793888
申请日：1988-07-05
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ISHIKAWA TAKAHARU , TAMURA AKIHIKO
IPC分类号： G06F13/00 , G06F11/34 , H04M3/22 , H04Q3/545
摘要： PURPOSE:To trace and record a transaction using state and storing content by detecting a transaction caught by a central controller by means of a bus tracing device without restricting the processing capacity of the central controller and storing area of a main memory device. CONSTITUTION:A bus tracing device 7 records the information transferred between a central controller 1 and main memory device 2 through a bus 4 and a transaction catch detecting means 100 in the device 7 detects that a transaction catching mechanism 11 in the central controller 1 catches an arbitrary vacant transaction 21. A caught transaction area setting means 200 extracts transaction position information held by the controller 1 in corresponding to the detection of the catching of the transaction 21 by the means 100 and sets the area to be occupied by the transaction 21 in the main memory device 2. A tracing means 300 performs tracing operations by recording the information transferred from the controller 1 in the set transaction area 21.

6. 发明专利

JPS63155249A INTER-EQUIPMENT COMMUNICATION SYSTEM 失效
公开(公告)号：JPS63155249A
公开(公告)日：1988-06-28
申请号：JP29999486
申请日：1986-12-18
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ISHIKAWA TAKAHARU , OKADA KATSUYUKI
IPC分类号： G06F13/14 , G06F13/20 , G06F13/362
摘要： PURPOSE:To improve the use efficiency of a common bus by reporting the acceptance state of commands from a transmission-side equipment from a reception-side equipment to the transmission-side equipment and releasing the common bus temporarily. CONSTITUTION:Plural equipment 1-1-1-n consisting of processors, etc., are connected through the common bus 2. The transmission-side equipment obtains the right to use the common bus 2 and sends a command to the reception-side equipment together with the numbers of the reception-side equipment and transmission-side equipment. When the reception-side equipment discriminates the reception-side equipment number and discriminates the command address to the reception-side equipment, it reports the reception state of the command to the transmisstion-side equipment and then releases the common bus 2 temporarily.

7. 发明专利

JPH09215073A CLOCK DISTRIBUTION SYSTEM 失效
公开(公告)号：JPH09215073A
公开(公告)日：1997-08-15
申请号：JP2093296
申请日：1996-02-07
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ISHIKAWA TAKAHARU , KUROKAWA KAZUKI
IPC分类号： H04Q11/04
摘要： PROBLEM TO BE SOLVED: To suppress an adverse influence caused by the stop of clock supply caused by the fault of a digital clock supplier or the interruption of power supply to a minimum when distributing a clock when selecting outputs from the duplex digital clock supplier concerning a clock distributing system for a telephone switchboard. SOLUTION: Respective clock distribution parts 2a and 2b of two systems, to which respectively correspondent one-side clock signals are supplied from two digital clock suppliers 1a and 1b, extract clock signals at plural frequencies from clock signals received by clock interface parts 3a and 3b. Selection parts 4a and 4b are controlled by control parts 6a and 6b and select any one of clock signals of two systems from the clock interface parts 3a and 3b of the present system and the other system, and clock parts 5a and 5b prepare the clocks required for present system devices from the outputs of the selection parts 4a and 4b. In an ordinary state, the selection parts 6a and 6b select the clock signals from the digital clock suppliers of present systems respectively correspondent to them under the control of the control parts 6a and 6b but when any abnormality is detected, the clock signals of the other systems are selected.

8. 发明专利

JPS56143067A MULTIPROCESSOR CONTROL SYSTEM 失效
公开(公告)号：JPS56143067A
公开(公告)日：1981-11-07
申请号：JP4412580
申请日：1980-04-04
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： SUYAMA MASATO , MASUO KAZUYUKI , ISHIKAWA TAKAHARU
IPC分类号： G06F12/00 , G06F12/16 , G06F13/16 , G06F15/16 , G06F15/177
摘要： PURPOSE:To prevent destruction of contents of a common device due to PC being in failure, by providing a plurality of control processors CPs and a duplex common device accessible commonly from said CPs with an operation mode memory means respectively for processing. CONSTITUTION:Means MC0, MC1, MP0-MPn storing the operating mode which indicates whether duplicated common memory devices 11, 12 must be operated in synchronism of both the systems or individually operated, are provided in the devices 11, 12 and CP0-CPn. If, CP0, for example, accesses to the devices 10, 11, the control signals like address and the like are added with the operation mode set to the means MC0 of the device itself and transmitted to the signal line 140. In the devices 11, 12, the control circuits CTL0, CTL1 collate the content of MC0, MC1 in the device of itself with the operation mode fed from CP0, and if they are in agreement, the access request is received, and if in disagreement, the disagreement signal is fed to CP0. Thus, if the devices 11, 12 are in synchronous operation, and even if CP in failure accesses in separation mode, the destruction of contents of the common device is avoided.

9. 发明专利

JP2013131655A Electronic device, slot identifier indication method, and electronic circuit unit 审中-公开
标题翻译：电子设备，槽识别器指示方法和电子电路单元
公开(公告)号：JP2013131655A
公开(公告)日：2013-07-04
申请号：JP2011280642
申请日：2011-12-22
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TAKAMURA ICHIRO , OSONE HISAO , ISHIKAWA TAKAHARU , KAKIHARA EIICHI
IPC分类号： H05K7/14
摘要： PROBLEM TO BE SOLVED: To provide an electronic device including an electronic circuit unit which, as an aspect thereof, acquires for indication a slot identifier in which slot itself is installed.SOLUTION: There is a plurality of slots, in each of which an electronic circuit unit 2 is installed. A slot number retention part of an electronic device retains slot numbers assigned to each of the plurality of slots. A slot number acquisition part 7 of the electronic circuit unit 2 acquires from the slot number retention part of the electronic device a slot number for the slot in which the electronic circuit unit 2 is installed. An external interface part 6 of the electronic circuit unit 2 indicates the acquired slot number.
摘要翻译：要解决的问题：提供一种包括电子电路单元的电子设备，该电子电路单元作为其一个方面获取用于指示其中本身被安装的时隙标识符。解决方案：存在多个时隙，每个时隙具有电子电路单元2安装。电子设备的槽号保持部分保留分配给多个时隙中的每一个的时隙号。电子电路单元2的槽号获取部分7从电子设备的槽号保持部分获取其中安装电子电路单元2的槽的槽号。电子电路单元2的外部接口部分6指示所获取的时隙号。

10. 发明专利

JPH064362A SYNCHRONOUS TRACE SYSTEM 失效
公开(公告)号：JPH064362A
公开(公告)日：1994-01-14
申请号：JP15710992
申请日：1992-06-17
申请人： FUJITSU LTD
发明人： ISHIKAWA TAKAHARU
IPC分类号： G06F11/34 , G06F15/16 , G06F15/177
摘要： PURPOSE:To synchronously trace plural processors concerning the synchronous trace system for an information collector to record the program running passage of plural processors. CONSTITUTION:Each information collection part 200 is provided with another starting means 400 to monitor the establishment of recording start conditions when conditions to start recording are set into the own information collection part 200, and to instruct the start of recording to all the information collection parts 200 when the establishment of recording start conditions is detected, and the lapsed time of recording is started to be counted and recorded in each information collection part 200. Otherwise, the lapsed time of recording counted in the own information collection part 200 is informed of all the other information collection parts 200 and recorded.

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