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    • 8. 发明专利
    • Interruption controlling system
    • 中断控制系统
    • JPS58192150A
    • 1983-11-09
    • JP7453482
    • 1982-05-06
    • Oki Electric Ind Co Ltd
    • ITOU KEIICHI
    • G06F13/24G06F9/48G06F13/26
    • G06F13/26
    • PURPOSE:To attain the efficient interruption processing having the flexibility in matching with a system, by setting a fixed priority as to a specific interruption request, and not fixing the priority as to another interrupting request. CONSTITUTION:When interruption request signals REQ1-REQ4 are generated, they are latched to an interruption request latch circuit 1 in synchronizing with a clock signal CLK to a request latch circuit 1. An output of the latch circuit 1 is applied to a priority control memory 2 as an address signal. Priority data a, b, c from the priority control memory 2 are set to an interruption control register 3 and applied to a request reception signal (ACK) transmission encoder 4 as BCD outputs a', b', c' together with the output of the latch circuit 1. Thus, any of the ACK signals ACK1-ACK4 in response to the priority selection data is transmitted to a central processing unit, and the efficient interruption processing is attained.
    • 目的:为了实现具有与系统匹配的灵活性的高效中断处理,通过对特定的中断请求设定固定的优先级,而不是固定关于另一中断请求的优先级。 构成:当产生中断请求信号REQ1-REQ4时,它们被锁存到与请求锁存电路1的时钟信号CLK同步的中断请求锁存电路1.锁存电路1的输出被施加到优先控制存储器 2为地址信号。 来自优先级控制存储器2的优先级数据a,b,c被设置为中断控制寄存器3,并且作为BCD输出a,b',c',并将其应用于请求接收信号(ACK)传输编码器4,并将其输出 锁存电路1.因此,响应于优先级选择数据的ACK信号ACK1-ACK4中的任一个被发送到中央处理单元,并且实现了有效的中断处理。