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1. 发明专利

JP2003101584A LINE ADAPTER DEVICE, PACKET EXCHANGE USING THE SAME, AUTOMATIC UPDATING METHOD OF TRANSMISSION INFORMATION TRANSCEIVER, AND ITS PROCESSING PROGRAM 审中-公开
公开(公告)号：JP2003101584A
公开(公告)日：2003-04-04
申请号：JP2001286879
申请日：2001-09-20
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , OKI ELECTRIC IND CO LTD
发明人： DOI YUKIHIRO , SAWADA OSAMU , TSUNODA MITSUHARU , TAKEUCHI TAKEHISA
IPC分类号： H04L12/70 , H04L29/10 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a line adapter device for performing an automatic updating processing of various set information about a transmission information transceiver, and a packet exchange using the same. SOLUTION: The line adapter device 130 according to the present invention comprises an interface 150 provided with the transmission information transceiver to be inserted therein, and a line adapter unit 160 having a memory unit 162 for memorizing configuration information of a first FPGA, and is equipped in the ATM exchange. The line adapter unit 160 comprises a collating unit 164 for collating a type of the transmission information transceiver whether or not being supported when the transmission information transceiver is inserted therein, a comparing unit 166 for comparing difference information whether or not to be existing between the configuration information of the first FPGA stored in the memory unit 162 and the configuration information of a second FPGA stored in the transmission information transceiver, and an updating unit 168 for updating the configuration information of the second FPGA after transmitting the difference information or the configuration information of the first FPGA itself to the transmission information transceiver.

2. 发明专利

JPH1056466A TRAFFIC LEVELING DEVICE IN ATM EXCHANGE SYSTEM 失效
公开(公告)号：JPH1056466A
公开(公告)日：1998-02-24
申请号：JP22459296
申请日：1996-08-08
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MIZUNO HIROYASU , TAKEUCHI TAKEHISA , ENDO YASUSHI , USHIJIMA SHIGEHIKO , NORITAKE KATSUSHI
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide the traffic leveling device in which the service is uniformly provided even when any virtual path is in use independently of a set band and no cell abort is caused. SOLUTION: The device 10 levels an operating band of cells transferred in an asynchronous transfer made(ATM) network over a plurality of kinds of virtual paths VP and virtual channels VC (logic channels) and transfers the leveled cells. Upon the receipt of cells 102 statistically multiplexed, the cells are stored tentatively in a cell memory 20 and the number of the stored input cells 102 is counted by an in-buffer cell number counter 28 corresponding to the logic channel. An output timing generating section 12 calculates an output enable time 126 corresponding to the operating band of the cells 102 corresponding to the logic channel in response to the increase/decrease in the count. Depending on the output enable time 126, the cells 102 are read from the cell memory 20 and sent. Thus, the cells 102 are sent at a uniform band in matching the traffic characteristic allowed by the opposite party equipment to be sent as to any logic channel.

3. 发明专利

JPH09244902A DOWNLOAD CIRCUIT 失效
公开(公告)号：JPH09244902A
公开(公告)日：1997-09-19
申请号：JP5447096
申请日：1996-03-12
申请人： OKI ELECTRIC IND CO LTD
发明人： UCHINO KENICHI , KIHARA KOICHI , TAKEUCHI TAKEHISA , ASO JIRO
IPC分类号： G06F15/16 , G06F9/06 , G06F9/445 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To externally download a program contents without turning off a power supply nor exchanging a program ROM even when a program change occurs in an operation mode, etc., by providing a specific memory, a specific processor and a specific program supply means and a specific control means respectively. SOLUTION: This circuit is provided with a processor 11 which is connected to a program reloadable memory via a bus and processes the program stored in the memory, a host CPU 14 which serves as a supply means to externally supply a program, and a control means 20. The means 20 is composed of a control circuit 15, a bidirectional buffer 16 and buffers 17 and 18. Then the means 20 connects the output line of the CPU 14 to the memory bus in a program rewrite mode to download the program of the CPU 14 to the processor 11 and then to transfer the downloaded program to the memory.

4. 发明专利

JPH11252122A ATM BUS CONNECTION SYSTEM 失效
公开(公告)号：JPH11252122A
公开(公告)日：1999-09-17
申请号：JP7141898
申请日：1998-03-05
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SAKAMOTO YOSHIMASA , TAKEUCHI TAKEHISA , GENDA KOICHI , MITSUBORI HIDEHIKO
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To built up a system by which asynchronous transfer mode ATM connection devices each having a different interface are interconnected and functions of each device are utilized. SOLUTION: An ATM termination device 10 is a single point connection device with a utopia level 1. A physical termination device 40 is a multi-point connection device with a utopia level 2. An ATM bus connection system 1 is provided with a cell multiplexer section 50 and a cell demultiplexer section 60. The cell multiplexer section 50 gives a line identification number to a cell received from the demultiplexer 40 and transfers the resulting cell to the demultiplexer 10. The cell demultiplexer section 60 refers to the line identification number in a cell received from the demultiplexer 10 and transfers the cell to the device with the level 2 corresponding to the device 40.

5. 发明专利

JPH11177571A SHAPING DEVICE 失效
公开(公告)号：JPH11177571A
公开(公告)日：1999-07-02
申请号：JP34554997
申请日：1997-12-15
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEUCHI TAKEHISA , NORITAKE KATSUSHI , USHIJIMA SHIGEHIKO
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/815 , H04L12/841 , H04L12/863 , H04L12/865 , H04L12/883
摘要： PROBLEM TO BE SOLVED: To provide a shaping device capable of storing plural VCs for the same time that can be outputted with simple constitution. SOLUTION: A time that can be outputted is decided to be one at most, concerning each VC at each time point. The device is provided with a schedule control part 14 with a chain pointer memory 141 storing a counter value showing the number of VCs by each time that can be outputted, a leading VC and a final VC, a chain memory 142 capable of storing VC of a cell to output second or after this, concerning the time that can be outputted in the state of a chain and an outputting time cue 143 for writing a present time when VC stored by designating the present time as the time that can be outputted exists.

6. 发明专利

JP2013131978A Transmission system, transmitter, receiver, transmission program, and reception program 有权
标题翻译：传输系统，发射机，接收机，传输方案和接收方案
公开(公告)号：JP2013131978A
公开(公告)日：2013-07-04
申请号：JP2011281379
申请日：2011-12-22
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： KONDO MASAHIRO , TAKEUCHI TAKEHISA , TERAYAMA TOMOYUKI , KUNIMASA TSUTOMU
IPC分类号： H04L1/00
摘要： PROBLEM TO BE SOLVED: To provide a transmission system capable of complying with a standardization technology of a line emulation of a time division multiplex signal, complementing packet loss data, and correcting shuffling of packet arrival sequence.SOLUTION: A transmission system according to the present invention includes: a transmitter which extracts one or more pieces of data from an input time division multiplex signal, assumes the extracted data as original data, assumes one or more pieces of data following in a time sequence of the original data as redundant data, writes on transmission memory means so that a data amount corresponds to a packet period, and reads each of the pieces of original data and each of the pieces of redundant data from a transmission memory; and a receiver which writes each of the pieces of original data and each of the pieces of redundant data on addresses starting from an address associated with a sequence number of a reception packet in order, and reads the respective pieces of data from the addresses successive in a predetermined period.
摘要翻译：要解决的问题：提供能够符合时分复用信号的线路仿真的标准化技术的传输系统，补充分组丢失数据，以及校正分组到达序列的混洗。解决方案：根据本发明的传输系统本发明包括：从输入时分多路复用信号中提取一条或多条数据的发送机，将所提取的数据作为原始数据，假设以原始数据的时间序列跟随的一条或多条数据为冗余数据，写入在传输存储器装置上，使得数据量对应于分组周期，并且从传输存储器读取每条原始数据和每条冗余数据; 以及从与接收包的序列号相关联的地址开始的地址上写入原始数据和每条冗余数据的接收器，并且从连续的地址中读取相应的数据片段预定时间。

7. 发明专利

JPH1056467A TRAFFIC SHAPING DEVICE 失效
公开(公告)号：JPH1056467A
公开(公告)日：1998-02-24
申请号：JP22600696
申请日：1996-08-08
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEUCHI TAKEHISA , ENDO YASUSHI , MIZUNO HIROYASU , USHIJIMA SHIGEHIKO , NORITAKE KATSUSHI
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/70 , H04L12/815 , H04L12/863
摘要： PROBLEM TO BE SOLVED: To facilitate timing control of a read/write cycle to a common cell buffer. SOLUTION: A buffer management section 4 discriminates whether or not an output cell 102 is in existence when an input cell 101 to a common cell buffer 1 is given. When the output cell 102 is in existence, a read address from the common cell buffer 1 is latched by a register 2. A memory access control section 11 uses a write address of the input cell 101 to be an address latched by a register 102 when the buffer management section 4 discriminates the presence of the output cell 102.

8. 发明专利

JPH09307581A BRIDGE 失效
公开(公告)号：JPH09307581A
公开(公告)日：1997-11-28
申请号：JP12138496
申请日：1996-05-16
申请人： OKI ELECTRIC IND CO LTD
发明人： TAKEUCHI TAKEHISA , KIHARA KOICHI , ASO JIRO , UCHINO KENICHI
IPC分类号： H04L12/46 , H04L12/70 , H04L12/28 , H04L12/56 , H04L12/66
摘要： PROBLEM TO BE SOLVED: To realize packet exchange processing by the hardware by comparing an added input port number with a registered output port number, selecting the output port number and adding it to a MAC packet. SOLUTION: An input port number addition circuit 11 provides a number NI specific to each port to a head of a MAC packet. An MUX 12 multiplex sequentially the MAC packets at a high speed and provides an output of the result to a shift register 13. The register 13 delays a time to provide a multiplex packet to an output port number addition circuit 14 by a prescribed time, a state machine 15 controls the circuit 14 and an associate memory 16 to obtain a port to output the MAC packet stored in the register 13. Then the MAC packet is given to output number filters 19 and passes only the filters 19 designated by an output port number NO and sent to a MAC sub-layer after speed adjustment by a buffer 20.

9. 发明专利

JPH09282194A SYSTEM SELECTION CONTROL METHOD, SYSTEM SELECTION CONTROLLER AND REDUNDANT SYSTEM 失效
公开(公告)号：JPH09282194A
公开(公告)日：1997-10-31
申请号：JP9103496
申请日：1996-04-12
申请人： OKI ELECTRIC IND CO LTD
发明人： KIHARA KOICHI , TAKEUCHI TAKEHISA , ASO JIRO , UCHINO KENICHI
IPC分类号： G06F11/20 , G06F15/16 , G06F15/163 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To reduce the number of signal lines required for connecting respective signal processing systems, to miniaturize the configuration of a hardware and to improve reliability by outputting one pattern signal corresponding to an operating state after switching through one signal line to the other signal processing system, switching and controlling the operating state of the other signal processing system. SOLUTION: When a controller 200 (or 210) of a low-order device switching the state according to the instruction of a maintenance device 1 as a high-order device is to report the switching of state of a present system to a controller 210 (or 200) of the other system paired with the present system, the width of a pulse to be sent through one signal line is switched corresponding to the state. Therefore, only by sending the pattern signal corresponding to the operating state after switching through one signal line to the other signal processing system, the switching generation of the operating state and the contents of the operating state after switching can be reported to the other signal processing system so that the required number of signal lines can be reduced to one.

10. 发明专利

JPH05199228A ROUTING SYSTEM FOR INTER-LAN CONNECTOR 失效
公开(公告)号：JPH05199228A
公开(公告)日：1993-08-06
申请号：JP890192
申请日：1992-01-22
申请人： OKI ELECTRIC IND CO LTD
发明人： YAJIMA YOSHIYUKI , TAKEUCHI TAKEHISA , MATSUSHITA ERIKO
IPC分类号： H04M3/00 , H04L12/28 , H04L12/66
摘要： PURPOSE:To simplify routing management on the public network side of an inter-LAN connector. CONSTITUTION:When an inter-LAN connector 2 receives data from a LAN 6 in the case of transmitting data from a LAN terminal 6a to a LAN terminal 9b, regardless of the value of the transmitting destination address of the LAN terminal 9b, the data are transmitted through a public network 1 to an inter- LAN connector 3 while setting the transmitting destination address to an address B of the inter-LAN connector 3 and setting the transmitting source address to an address A of the inter-LAN connector 2 without any condition. The inter- LAN connector 3 detects the transmitting destination address B of the LAN and retrieves whether this address is existent in a LAN 7 managed by the own device and when the absence is confirmed, the data are transmitted through the public network 1 to an inter-LAN connector 4 while setting the transmitting destination address to an address C of the inter-LAN connector 4 and setting the transmitting source address to the address B of the inter-LAN connector 3. Inter-LAN connectors 4 and 5 are similarly processed as well.

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