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1. 发明专利

JP2009038241A Component accommodating wiring board, capacitor for accommodating wiring board 有权
标题翻译：配件接线板，接线板电容器
公开(公告)号：JP2009038241A
公开(公告)日：2009-02-19
申请号：JP2007201975
申请日：2007-08-02
申请人： Ngk Spark Plug Co Ltd , 日本特殊陶業株式会社
发明人： HIGO ICHIEI , HIRANO SATOSHI , OKUYAMA MASAHIKO , SATO MANABU
IPC分类号： H05K3/46 , H01G4/12 , H01G4/30 , H01L23/12
CPC分类号： H01L2224/16237 , H01L2924/1461 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a component accommodating wiring board capable of preventing crack by mitigating a stress generated in a state that components are accommodated in the wiring board. SOLUTION: The wiring board 10 includes a core substrate 11, a ceramic capacitor 101 and a wiring lamination unit 31. A hold hole 90 for holding ceramic capacitor 101 is formed on the core substrate 11. The ceramic capacitor 101 has stress mitigating layers 151 formed on the main surface 102 of capacitor, on the rear surface 103 of capacitor and on the side surfaces 106 of capacitor. The stress mitigating layer 151 mitigates an external stress applied on the surfaces of the ceramic capacitor 101 under a state that the ceramic capacitor 101 is accommodated in the wiring substrate 10. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够通过减轻在组件容纳在布线板中的状态下产生的应力来防止裂纹的部件容纳布线板。布线板10包括芯基板11，陶瓷电容器101和布线层叠单元31.在芯基板11上形成有用于保持陶瓷电容器101的保持孔90.陶瓷电容器101具有减轻应力形成在电容器的主表面102上的层151，电容器的背面103和电容器的侧表面106上。应力缓和层151在陶瓷电容器101容纳在布线基板10中的状态下减轻施加在陶瓷电容器101的表面上的外部应力。（C）2009，JPO＆INPIT

2. 发明专利

JP2005197285A Multilayer ceramic substrate and its manufacturing method 有权
标题翻译：多层陶瓷基板及其制造方法
公开(公告)号：JP2005197285A
公开(公告)日：2005-07-21
申请号：JP2003435171
申请日：2003-12-26
申请人： Ngk Spark Plug Co Ltd , 日本特殊陶業株式会社
发明人： TAKAHASHI HIROYUKI , KATAGIRI HIROYUKI , SATO MANABU , OKUYAMA MASAHIKO
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer ceramic substrate which does not contain Pb, effectively suppresses a contraction in a manufacturing time while holding dielectric characteristics, and easily removes a contraction suppressing layer, and also to provide a method of manufacturing the same.
SOLUTION: The multilayer ceramic substrate having a glass ceramics blending part includes a glass phase consisting of glass having: transition point of 580-700°C; a temperature difference between the glass transition point and a softening point of 140°C or lower; and a content of 0-1 mass% Pb in terms of an oxide. The method of manufacturing the substrate includes a step of baking an unbaked sheet containing a ceramic filler and a glass powder without pressurization the contraction suppressing layer on the front and rear surfaces of a laminate obtained by laminating the unburned sheets. In the method, the glass powder has the glass transition point of 580-700°C, the temperature difference between the glass transition point and the softening point of 140°C or lower, and the glass that the content of Pb is 1 mass% or less (including "0") in terms of the oxide, is used.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供不含Pb的多层陶瓷基板，在保持介电特性的同时有效抑制制造时间的收缩，容易除去收缩抑制层，并且还提供制造方法相同。＆lt; P＆gt;解决方案：具有玻璃陶瓷配合部的多层陶瓷基板包括由玻璃构成的玻璃相，其转变点为580〜700℃; 玻璃化转变点与软化点之间的温度差为140℃以下; 以氧化物换算为0〜1质量％的Pb。制造基板的方法包括如下步骤：将不含有陶瓷填料和玻璃粉末的未烘烤片材加压而不加压通过层压未燃烧片材得到的层压板的前后表面的收缩抑制层。在该方法中，玻璃粉末的玻璃化转变点为580-700℃，玻璃化转变温度与软化点的温度差为140℃以下，Pb含量为1质量％或更少（包括“0”）。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005129918A Ceramic substrate for thin film electronic component and thin film electronic component using this 有权
标题翻译：薄膜电子元件和薄膜电子元件的陶瓷基板
公开(公告)号：JP2005129918A
公开(公告)日：2005-05-19
申请号：JP2004285180
申请日：2004-09-29
申请人： Ngk Spark Plug Co Ltd , 日本特殊陶業株式会社
发明人： ICHIYANAGI SEIJI , OTSUKA ATSUSHI , SATO MANABU , OKUYAMA MASAHIKO
IPC分类号： H01G4/12 , H05K1/11 , H05K3/28
摘要： PROBLEM TO BE SOLVED: To provide a ceramic substrate for a thin film electronic component equipped with a circuit pattern in a glaze layer, and thin film electronic component using the substrate. SOLUTION: This substrate is equipped with a ceramic substrate 2, glaze layer 3 formed on at least one surface of the substrate, and circuit pattern 21 arranged inside the layer 3 with the part of the pattern exposed over the surface of the layer 3. This circuit pattern 21 can be extended inside the ceramic substrate 2 and the part of the pattern can be exposed to the other surface of the ceramic substrate 2. The thickness of the layer 3 can be from 10 to 100 μm. The surrender point of the layer 3 can be 700°C or over. The principal components of glass that constitutes the layer 3 can be Si, Al, B, Ca and O. The layer 3 can be obtained by heat and pressure treatment of a glass layer 24 formed on the frontal surface of the ceramic substrate 2. This thin film electronic component is equipped with this substrate. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于在釉层中配备电路图案的薄膜电子部件的陶瓷基板和使用该基板的薄膜电子部件。解决方案：该基板装备有陶瓷基板2，形成在基板的至少一个表面上的釉层3和布置在层3内的电路图案21，其中图案的一部分暴露在层的表面上该电路图案21可以在陶瓷基板2内部延伸，并且图案的一部分可以暴露于陶瓷基板2的另一个表面。层3的厚度可以为10至100μm。第3层的投降点可以为700°C以上。构成层3的玻璃的主要成分可以是Si，Al，B，Ca和O.层3可以通过对形成在陶瓷基板2的前表面上的玻璃层24进行热处理和压力处理来获得。薄膜电子部件配备有该基板。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2011014882A Ceramic capacitor and wiring board 有权
标题翻译：陶瓷电容器和接线板
公开(公告)号：JP2011014882A
公开(公告)日：2011-01-20
申请号：JP2010121051
申请日：2010-05-26
申请人： Ngk Spark Plug Co Ltd , 日本特殊陶業株式会社
发明人： ICHIYANAGI SEIJI , MURAKAMI KENJI , SATO MOTOHIKO , OTSUKA ATSUSHI , OKUYAMA MASAHIKO
IPC分类号： H01G4/12 , H01G2/06 , H01G4/30 , H05K1/18 , H05K3/46
CPC分类号： H05K1/0231 , H01G4/232 , H01G4/30 , H01G4/33 , H01L23/49822 , H01L23/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/09701 , H05K1/185 , H05K3/4602 , H05K2201/10712 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a ceramic capacitor which can prevent the generation of cracks when being built in a wiring board.SOLUTION: A capacitor body 104 of the ceramic capacitor 101 includes a first laminated portion 107 and second laminated portions 108, 109. The first laminated portion 107 is formed by alternately stacking a ceramic dielectric layer 105 and inner electrodes 141, 142. The second laminated portions 108, 109 are disposed so as to be exposed on capacitor main surfaces 102, 103 of the capacitor body 104. The second laminated portions 108, 109 have corners 154, 155 as boundaries between the capacitor main surfaces 102, 103 and the capacitor side surface 106, respectively. Metal layers 171, 172 for covering the corners 154, 155 are formed on the outer surface of the capacitor body 104.
摘要翻译：要解决的问题：提供一种陶瓷电容器，其可以防止在内置在布线板中时产生裂纹。解决方案：陶瓷电容器101的电容器主体104包括第一层叠部分107和第二层叠部分108,109。第一层叠部分107通过交替堆叠陶瓷电介质层105和内部电极141,142而形成。第二层叠部分108,109被设置为暴露在电容器主体104的电容器主表面102,103上。第二层叠部分108,109分别具有作为电容器主表面102,103和电容器侧表面106之间的边界的角部154,155。用于覆盖角部154,155的金属层171,172形成在电容器主体104的外表面上。

5. 发明专利

JP2010010394A Ceramic wiring board 有权
标题翻译：陶瓷接线板
公开(公告)号：JP2010010394A
公开(公告)日：2010-01-14
申请号：JP2008167998
申请日：2008-06-26
申请人： Ngk Spark Plug Co Ltd , 日本特殊陶業株式会社
发明人： OGAWA TAKAMICHI , YAMAMOTO HIROSHI , HIRANO SATOSHI , OTSUKA ATSUSHI , OKUYAMA MASAHIKO
IPC分类号： H05K3/46 , H05K1/09
摘要： PROBLEM TO BE SOLVED: To provide a ceramic wiring board which has a superior mounting strength and has a low electric resistance for a conductor portion and which can be manufactured without suffering warping, peeling, or the like caused by simultaneous firing. SOLUTION: The ceramic wiring board 10 includes a ceramic substrate 11, chief of which is ceramic that sinters at a temperature higher than the melting point of copper, and conductors 18, 19, 23, 27, and 28 which are formed in the ceramic substrate 11. The conductors 18, 19, 23, 27, and 28 each consist of a mixed phase of a filler and copper. The filler is formed mainly of chromium-based inorganic metal oxide having a melting point higher than that of copper. The content of the inorganic metal oxide in the filler is not less than 10 vol.% nor more than 60 vol.%. A preferred inorganic metal oxide in the filler is, for example, a chromium oxide or a copper-chromium composite oxide. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有优良的安装强度并且对于导体部分具有低电阻并且可以在不受同时烧制引起的翘曲，剥离等的情况下制造的陶瓷布线板。＆lt; P＆gt;解决方案：陶瓷布线板10包括陶瓷基板11，其主要是在高于铜的熔点的温度下烧结的陶瓷，以及导体18,19,23,27和28，其形成在陶瓷基板11.导体18,19,23,27和28各自由填料和铜的混合相组成。填料主要由熔点高于铜的铬基无机金属氧化物形成。填料中无机金属氧化物的含量不小于10vol。％，也不大于60vol％。填料中优选的无机金属氧化物是例如氧化铬或铜 - 铬复合氧化物。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2010177508A Method for manufacturing multilayer ceramic electronic component 有权
标题翻译：制造多层陶瓷电子元件的方法
公开(公告)号：JP2010177508A
公开(公告)日：2010-08-12
申请号：JP2009019524
申请日：2009-01-30
申请人： Ngk Spark Plug Co Ltd , 日本特殊陶業株式会社
发明人： MURAKAMI KENJI , SATO MOTOHIKO , OTSUKA ATSUSHI , OKUYAMA MASAHIKO
IPC分类号： H01G4/30 , H01G4/12
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer ceramic electronic component capable of surely forming a via conductor in the successful shape since a through hole with high perpendicularity and high taper ratio can be formed. SOLUTION: In the method for manufacturing the multilayer ceramic electronic component 101, the through hole 130 is formed on a laminate 220 by a laser machining process. In the process, a system for controlling an irradiating position via an optical system 303 on which a laser beam 250 is reflected and converged is adopted. The maximum width of a machining area which can be controlled via the optical system 303 is set to ≤50 mm. Focal distance of the laser beam 250 is set to ≥70 mm, focal depth of the laser beam 250 is set to ≥70 μm, and wavelength of the laser beam 250 is set to ≥2 μm and ≤20 μm. As an irradiation system of the laser beam 250, a pulse system is used, and pulse width is set to ≥15μsec and ≤150μsec. When the laser beam is irradiated at a specific hole forming position P1 for n times, irradiation for n times is not continuously performed to specific hole forming positions P2-P5. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够形成通孔导体成功形成的多层陶瓷电子部件的方法，因为可以形成具有高垂直度和高锥度比的通孔。解决方案：在多层陶瓷电子部件101的制造方法中，通过激光加工工艺在层压板220上形成通孔130。在该过程中，采用用于通过激光束250反射和收敛的光学系统303来控制照射位置的系统。可以通过光学系统303控制的加工区域的最大宽度设定为≤50mm。激光束250的焦距设定为≥70mm，激光束250的焦点深度设定为≥70μm，激光束250的波长设定为≥2μm，≤20μm。作为激光束250的照射系统，使用脉冲系统，脉冲宽度设定为≥15μsec，≤150μsec。当激光束在特定孔形成位置P1照射n次时，对特定的孔形成位置P2-P5不连续进行n次的照射。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010034256A Electrostatic chuck 有权
标题翻译：静电卡
公开(公告)号：JP2010034256A
公开(公告)日：2010-02-12
申请号：JP2008194434
申请日：2008-07-29
申请人： Ngk Spark Plug Co Ltd , 日本特殊陶業株式会社
发明人： INUI YASUHIKO , TSUJI MASAKI , ITO YOICHI , SUGIURA HIROKI , MORITA NAOTOSHI , OKUYAMA MASAHIKO
IPC分类号： H01L21/683 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To provide an electrostatic chuck that never varies in leak amount of cooling gas even when a large-sized body to be sucked is repeatedly attached and detached to maintain uniform controllability for a temperature distribution of a suction surface by the cooling gas, and then enhances uniformity, reproducibility, and yield of processing such as etching processing on the body to be sucked and so on. SOLUTION: The electrostatic chuck 10 includes an insulating plate 11 having the suction surface 13 for sucking and fixing the body to be sucked, and an electrostatic electrode 12 provided in the insulating plate 11, wherein the insulating plate 11 is formed of ceramic having a Young's modulus of 100 to 200 GPa and surface roughness (Ra) of the suction surface 13 is 1 to 2 μm. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种静电卡盘，即使当被吸引的大型体被重复地附接和分离以保持对吸入表面的温度分布的均匀控制性时，也不会改变冷却气体的泄漏量，冷却气体，然后提高加工的均匀性，再现性和加工性能，例如待吸附的身体上的蚀刻加工等。解决方案：静电吸盘10包括具有用于吸引和固定被吸收体的吸附表面13的绝缘板11和设置在绝缘板11中的静电电极12，其中绝缘板11由陶瓷杨氏模量为100〜200GPa，吸附面13的表面粗糙度（Ra）为1〜2μm。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2009212484A Via array type multilayer ceramic capacitor and method of manufacturing the same, and wiring board with built-in capacitor 有权
标题翻译：通过阵列型多层陶瓷电容器及其制造方法和具有内置电容器的接线板
公开(公告)号：JP2009212484A
公开(公告)日：2009-09-17
申请号：JP2008166867
申请日：2008-06-26
申请人： Ngk Spark Plug Co Ltd , 日本特殊陶業株式会社
发明人： OGAWA TAKAMICHI , YAMAMOTO HIROSHI , HIRANO SATOSHI , OTSUKA ATSUSHI , OKUYAMA MASAHIKO
IPC分类号： H01G4/30 , H01G4/12 , H01L23/12 , H01L23/15 , H05K3/46
CPC分类号： H01L2224/16225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide a via array type multilayer ceramic capacitor which has higher capacity, higher reliability, lower inductance, and lower electric resistance, and is suitable for use in decoupling.
SOLUTION: The via array type multilayer ceramic capacitor 10 comprises a capacitor body 104, a plurality of via conductors 131 and 132, a plurality of internal-layer electrodes 141 and 142, a plurality of external electrodes 111 and 112, etc. The capacitor body 104 is formed by stacking and arranging the plurality of internal-layer electrodes made principally of nickel through a dielectric 105 made principally of barium titanate. The plurality of via conductors 131 and 132 consist of a mixed phase of a filler, made principally of an inorganic metal compound which is metal that belongs to the group V or VI of the periodic table and has a higher fusion point than barium titanate, and copper.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有更高容量，更高可靠性，更低电感和更低电阻的通孔阵列型多层陶瓷电容器，并且适用于去耦。解决方案：通孔阵列型多层陶瓷电容器10包括电容器主体104，多个通孔导体131和132，多个内层电极141和142，多个外部电极111和112等。电容器主体104通过主要由钛酸钡制成的电介质105堆叠并排列主要由镍制成的多个内层电极而形成。多个通孔导体131和132由填料的混合相组成，主要由属于元素周期表第Ⅴ或Ⅵ族的金属的无机金属化合物构成，熔点比钛酸钡高; 铜。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2003069229A Multilayer printed wiring board 审中-公开
标题翻译：多层印刷接线板
公开(公告)号：JP2003069229A
公开(公告)日：2003-03-07
申请号：JP2001255779
申请日：2001-08-27
申请人： Ngk Spark Plug Co Ltd , 日本特殊陶業株式会社
发明人： SUMI YASUSHI , KOJIMA TOSHIFUMI , OKUYAMA MASAHIKO , IGAI NORIHIKO
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To obtain a multilayer printed wiring board containing an electronic component which prevents a crack from occurring in an insulating layer laminat ed and formed on a through hole or a solder resist layer in a reliability evaluat ing test (particularly a thermal impact test of repeating cooling to -55 deg.C and heating to 125 deg.C), which improves electric characteristics by reducing a parasitic capacity and which lowers a back surface height. SOLUTION: The multilayer printed wiring board comprises a build-up layer having insulating layers and wiring layers alternatively laminated on at least one surface of a core board and openings and through-holes formed so as to pass through the core board and the build-up layer. In the substrate, an electronic component is disposed in the opening, and embedded by using the embedding resin. A cured material of a paste or filling in the through-hole having an absolute value of a difference of a thermal expansion coefficient of a thickness direction (Z-axis direction) of the core board of 20 ppm/ deg.C or lower is filled in the through-hole. An elastic modulus of the cured material of the paste at 25 deg.C is desirably in a range of 3.0 to 6.5 GPa.
摘要翻译：要解决的问题：为了获得包含电子部件的多层印刷线路板，其在可靠性评估试验（特别是热冲击）中，防止在层压并形成在通孔或阻焊层上的绝缘层中发生裂纹重复冷却至-55℃并加热至125℃的试验），其通过降低寄生容量并降低背表面高度来改善电特性。解决方案：多层印刷线路板包括：堆叠层，其具有绝缘层和交替层压在芯板的至少一个表面上的布线层，并且开口和通孔形成为穿过芯板和积聚层层。在基板中，将电子部件设置在开口内，并通过使用嵌入树脂嵌入。将填充在芯板的厚度方向（Z轴方向）的热膨胀系数的绝对值的绝对值为20ppm /℃以下的通孔中的糊状物填充固化物填充在通孔中。糊状物在25℃下的固化物的弹性模量优选为3.0〜6.5GPa的范围。

10. 发明专利

JP2010258195A Method of manufacturing piezoelectric element 审中-公开
标题翻译：制造压电元件的方法
公开(公告)号：JP2010258195A
公开(公告)日：2010-11-11
申请号：JP2009106088
申请日：2009-04-24
申请人： Ngk Spark Plug Co Ltd , 日本特殊陶業株式会社
发明人： IWASAKI MASATAKA , YASUDA HIROYA , TAKAYAMA YASUSHI , OTSUKA ATSUSHI , OKUYAMA MASAHIKO
IPC分类号： H01L41/083 , F02M51/00 , F02M51/06 , H01L41/187 , H01L41/22 , H01L41/297 , H01L41/39 , H02N2/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a piezoelectric element in which an organic binder is made easy to be removed (degreasing) even when oxygen partial pressure is low, and the time needed for the degreasing is shortened while suppressing oxidation of Cu. SOLUTION: In the method of manufacturing the piezoelectric element 10 formed by alternately laminating a piezoelectric ceramic layer 2 consisting essentially of lead zirconate titanate and Cu-based electrode layers 4, 6 consisting essentially of Cu, a calcined powder having the specific surface area of 0.75 to 1.64 m 2 /g is obtained by adding an additive material containing at least one of Mn and Co to a material powder prepared by mixing respective powders of Pb (lead) oxide, Ti (titanium) oxide and Zr (zirconium) oxide, and calcinating and pulverizing the mixture, and an unbaked piezoelectric element 10x is obtained by forming and baking an unbaked piezoelectric ceramic layer 2x from a preparation material having an organic binder added to the calcined powder, and then alternately laminating unbaked Cu-based electrode layers 4x, 6x serving as the Cu-based electrode layers after the baking, and the unbaked piezoelectric element is degreased in an atmosphere of ≤1.013 Pa in oxygen partial pressure. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供即使在氧分压低的情况下也容易除去有机粘合剂（脱脂）的压电元件的制造方法，并且在抑制脱脂所需的时间被缩短的同时抑制 Cu的氧化。解决方案：在通过交替层叠基本上由锆钛酸铅组成的压电陶瓷层2和基本上由Cu组成的Cu基电极层4,6形成的压电元件10的制造方法中，具有比表面积的煅烧粉末通过将含有至少一种Mn和Co的添加剂材料添加到通过混合Pb（铅）氧化物，Ti（钛）的各种粉末而制备的材料粉末中来获得0.75至1.64μm的面积）氧化物和Zr（锆）氧化物，并煅烧和粉碎混合物，通过从预煅烧粉末中添加有机粘合剂的制备材料形成并烘焙未烘烤的压电陶瓷层2x，得到未烘烤的压电元件10x，然后在烘烤后交替层叠用作Cu基电极层的未焙烧的Cu基电极层4x，6x，并将未烘烤的压电元件在≤1.013Pai的气氛中脱脂 n氧分压。版权所有（C）2011，JPO＆INPIT

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