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1. 发明专利

JPS60217775A DATA TRANSFER CIRCUIT 失效
公开(公告)号：JPS60217775A
公开(公告)日：1985-10-31
申请号：JP7436684
申请日：1984-04-13
申请人： NIPPON TELEGRAPH & TELEPHONE , SONY CORP
发明人： KATAGIRI KOUICHI , UENISHI TOSHIFUMI , MAEDA SATORU , MOTOKI KAZUO , TANIGUCHI IKUO
IPC分类号： G06F3/12 , G06F5/06 , G06F13/36 , G06F13/38 , H04N7/00
摘要： PURPOSE:To reduce the number of interrupts to a CPU to shorten the CPU processing time by issuing a bus request to the CPU in accordance with the address of every unit of a counter, which generates a read address of a buffer memory, to interrupt the CPU. CONSTITUTION:Every one-line components of character picture data written in a video RAM are stored in a work RAM21 by the control of a CPU22. When a print start signal PS is supplied from the CPU22 to a J-K F/F30, a signal S30 goes to the high level, and counting of print clocks CCK is started in an octal counter 33. Bus release is requested from a D-FF44 to the CPU22 by the carry output of the octal counter 33, and the CPU22 sets the control signal to the high- impedance state after termination of the executing instruction when receiving this bus release request. Thus, character picture data of the next line is stored in the work RAM21 when the CPU22 is interrupted.

2. 发明专利

JPH0644818B2 失效
公开(公告)号：JPH0644818B2
公开(公告)日：1994-06-08
申请号：JP7436584
申请日：1984-04-13
申请人： NIPPON TELEGRAPH & TELEPHONE , SONY CORP
发明人： KATAGIRI KOUICHI , HANAMOTO YOSHIHIRO , MAEDA SATORU , TANIGUCHI IKUO
IPC分类号： G09G5/18 , H04N7/16 , H04N7/173

3. 发明专利

JPS60217779A SIGNAL GENERATING CIRCUIT 失效
公开(公告)号：JPS60217779A
公开(公告)日：1985-10-31
申请号：JP7436584
申请日：1984-04-13
申请人： NIPPON TELEGRAPH & TELEPHONE , SONY CORP
发明人： KATAGIRI KOUICHI , HANAMOTO YOSHIHIRO , MAEDA SATORU , TANIGUCHI IKUO
IPC分类号： G09G5/18 , H04N7/16 , H04N7/173
摘要： PURPOSE:To attain always a display clock signal and a horizontal synchronizing signal in certain phase relations by detecting the point where the phase difference between a chrominance subcarrier and the display clock signal is a prescribed value and controlling the operation of a synchronizing signal generator by this detection output. CONSTITUTION:When a power source is turned on, a J-K F/F14 is set to the clear state, and a signal SQ is supplied to the reset terminal of a synchronizing signal generating circuit 2' from an output terminal Q. The signal SQ sets a J-K F/F18 to the clear state to inhibit the output of display clocks CLK from the output terminal. When the operation of a PLL circuit consisting of an oscillator 6, a phase comparator 5, etc. is stabilized, output ''1'' is obtained from a timer circuit 11, and thereby, the output SQ of the J-K F/F14 goes to high level ''1'' to start the operation of the synchronizing signal generating circuit 2'. Simultaneously, the clear state of the J-K F/F18 is released by the signal SQ, and the display clock signal CLK of 5.727MHz is outputted from the output terminal Q.

4. 发明专利

JPS6076813A PLL CIRCUIT 失效
公开(公告)号：JPS6076813A
公开(公告)日：1985-05-01
申请号：JP18562983
申请日：1983-10-04
申请人： NIPPON TELEGRAPH & TELEPHONE , SONY CORP
发明人： KATAGIRI KOUICHI , NODA KAZUAKI , MAEDA SATORU , TANIGUCHI IKUO
IPC分类号： H03L7/10 , H03L3/00 , H03L7/199
摘要： PURPOSE:To obtain a phase locked device instantaneously regardless of an initial state by starting a counting action synchronously with a comparison signal for a dividing counter with which a phase comparison error signal with a comparison signal is turned into the control voltage of a voltage control oscillator. CONSTITUTION:A horizontal synchronizing signal HD supplied to a terminal 1 as a comparison signal is supplied to a phase comparator 2 to obtain a comparison error signal with the oscillation signal of a voltage control oscillator 3 which is divided by a dividing counter 4'. This error signal is supplied to the oscillator 3 as the control voltage via an LPF5. The positive DC voltage +B is supplied to a power supply terminal 8 when a power supply is applied. Therefore the signal obtained at a joint P is set at 0 for a period decided by a resistor 9 and a capacitor 10. Then the counter 4' starts its counting action at a trailling time point of the signal HD.

5. 发明专利

JPH05292113A 失效
公开(公告)号：JPH05292113A
公开(公告)日：1993-11-05
申请号：JP8743792
申请日：1992-04-09
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TANIGUCHI IKUO , UEDA HIROMI , AKUTSU KENJI
IPC分类号： H04Q11/04 , H04L12/48
摘要： PURPOSE:To avoid cell abort by providing a generating means of path supervisory information with identification information representing a source redundancy system inserted thereto to a generation point of path supervisory information and providing a termination means used when its own system is dissident with the source redundancy system based on the identification information to an intermediate detection point. CONSTITUTION:A Pi generating means 21 at a generation point A of path supervisory information (Pi) generates the information Pi including identification information representing a source redundancy system of the Pi. A 2nd normality discrimination means 22 placed at an intermediate detection point B of the Pi discriminates whether or not a path is normal based on the detected Pi. A 1st Pi termination means 23 terminates the detected Pi when its own system and a Pi source redundancy system are dissident based on the identification information included in the detected Pi. A 2nd normality discrimination means 24 at a Pi final detection point C discriminates whether or not a path is normal based on the detected Pi and a 2nd Pi termination means 25 terminates the detected Pi. Thus, one Pi is supplied to the points B,C and cell abort due to concentrated Pi information sets is avoided.

6. 发明专利

JPH08293865A SIGNAL PATH MONITOR 失效
公开(公告)号：JPH08293865A
公开(公告)日：1996-11-05
申请号：JP9553195
申请日：1995-04-20
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TEZUKA KOJI , AMAMIYA SHIGEO , TANIGUCHI IKUO , IINO TOSHIYUKI , YOSHIZAWA JINICHI , MATSUNAGA HARUHIKO
IPC分类号： H04Q3/00 , H04L12/26 , H04L12/28 , H04L12/70
摘要： PURPOSE: To efficiently monitor a signal path by means of a small-scale equipment through the use of the idle time of the signal path by testing test signals in the order of the signal path and controlling a testing order by time-division control concerning each operation of outputting the result. CONSTITUTION: A test cell generation means 10 outputs a test cell generated by a test pattern generation part 100 and a path changing table 500 to a test cell checking means 80 through the signal path of an object to be tested 12. When the test pattern checking part 200 of the means 80 checks this test cell and detects abnormality in the signal path, a monitoring alarm within a package is outputted. A test scheduling function part 600 time-division-controls each operation of means 70 and 80 and controls the order of the test to test the signal path in order through the use of the idle time of operation. A path monitor for monitoring the interval between packages 60 outputs the output of the object to be tested 12 to a transmission line with the specified timing of a free cell detection part 710. Thereby, the signal path is efficiently monitored by a small-scale equipment.

7. 发明专利

JPH0669923A ALARM STATE MANAGEMENT EQUIPMENT 失效
公开(公告)号：JPH0669923A
公开(公告)日：1994-03-11
申请号：JP21778592
申请日：1992-08-17
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： FUJII TAIKI , TEZUKA KOJI , AMAMIYA SHIGEO , NAKAJO TAKAFUMI , TANIGUCHI IKUO , TANIGUCHI MITSUKI , KANAYAMA YUKIHARU , UEDA HIROMI
IPC分类号： H04M3/08 , H04L12/24 , H04L12/26
摘要： PURPOSE:To provide a fault state management equipment implementing the processing only of an alarm signal especially with higher priority so as to simplify the processing content with respect to management equipment of the alarm state generated due to a fault of a transmission line and a communication equipment or the like. CONSTITUTION:The management equipment is made up of an alarm information identification means 2 identifying alarm information among information sets via a communication path and selecting the identified information, an alarm class discrimination means 3 to discriminate an alarm class from the alarm information identified and selected thereby, a priority discrimination means 4 discriminating the priority of the alarm class from the alarm class discrimination means 3 and of the alarm class stored in an alarm state management means 5 and outputting the alarm class with higher priority, and an alarm state management means 5 revising the stored content into the consecutive alarm class for a prescribed number of times and raising the alarm notice when the alarm class from the priority discrimination means 4 different from the preceding alarm class is consecutive for a prescribed number of times.

8. 发明专利

JPH04369945A ATM CROSS CONNECTOR 失效
公开(公告)号：JPH04369945A
公开(公告)日：1992-12-22
申请号：JP14610991
申请日：1991-06-18
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TANIGUCHI IKUO , NARITA KENJI , HASHIMOTO KENICHI
IPC分类号： H04L12/26
摘要： PURPOSE:To check the normality of a main signal setting area used for VPI conversion of an ATM cell for an active signal actually in a VPI conversion table. CONSTITUTION:A VPI conversion table 1 has a traffic flag 2 and rewrites a setting value of an output path VPI of the table 1 corresponding to an input path VPI to be checked when the flag 2 is set to 0, and the read output path VPI is set as a comparison reference of the output path VPI when the flag 2 is set to 1 and the output path VPI read from the table 1 is dissident with the output path VPI to be set for check, and the read output path VPI is set as a comparison reference value when the flag 2 is set to 0 or the read output path VPI is coincident with the output path VPI to be set.

9. 发明专利

JPH05292118A 失效
公开(公告)号：JPH05292118A
公开(公告)日：1993-11-05
申请号：JP9468292
申请日：1992-04-15
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP , HITACHI LTD
发明人： TANIGUCHI IKUO , HANAOKA SUSUMU , OTA HIROSHI , UEDA HIROMI , KURANO TAKANORI , NISHIHARA MOTOO , ASHI MASAHIRO , NAKANO YUKIO
IPC分类号： H03M13/00 , H04L12/24 , H04L12/26 , H04L12/48
摘要： PURPOSE:To reduce the scale of the circuit and to decrease a delay in a line with respect to the transmission quality supervisory system in the transmitter/ receiver and communication system for the communication employing the ATM system. CONSTITUTION:A transmitter 310 is configured such that when a user cell number reaches a required number and an idle cell detection section 220 detects an idle cell, an output section 105 inserts the result from the calculation for error supervision for each transmission path (VP) at a transmission arithmetic operation section 100 to an idle cell based on a control signal outputted from a cell number variable control section 250 and sends the result as a supervisory OAM cell. Furthermore, a receiver 320 uses an error discrimination section 200 to compare the result obtained by the arithmetic operation for error supervision as to a block separated by an OAM cell received by a reception arithmetic operation section 110 with the result of arithmetic operation extracted from the OAM cell received by a reception information extract section 180 thereby implementing error supervision to a cell string of variable length.

10. 发明专利

JPH07147569A INSERTION CIRCUIT FOR MONITOR DATA 失效
公开(公告)号：JPH07147569A
公开(公告)日：1995-06-06
申请号：JP29229893
申请日：1993-11-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HASEGAWA HITOSHI , TANIGUCHI IKUO , OTA HIROSHI , UEDA HIROMI
IPC分类号： H04J3/12 , H04J3/14
摘要： PURPOSE:To maximize number of data insertion circuits within a predetermined time by inserting monitor data within a predetermined period and keeping an entire average monitoring data insertion period to be a predetermined period of a valid frame. CONSTITUTION:The circuit has a count section 10, a data insertion section 30, and an alarm detection section 20, the count section 10 receives an enable signal and a data insertion end flag and outputs carry-out for each N-th valid frame and sends a data insertion enable flag set for each N valid frame or cleared in a data insertion end flag. The data insertion section 30 receives the data insertion enable flag and inserts monitor data to a first idle frame while the data insertion enable flag continues the set state and sends the data insertion end flag. The alarm detection section 20 outputs an alarm set when carry-out is received when the data insertion enable flag is set and cleared when the data insertion end flag is received.

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