专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS5230303A SYNCHRONOUS TERMINAL CONNECTION METHOD 失效
公开(公告)号：JPS5230303A
公开(公告)日：1977-03-08
申请号：JP10663475
申请日：1975-09-03
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD , OKI ELECTRIC IND CO LTD , HITACHI LTD
发明人： MIKI YASUO , NANGAKU MASAKAZU , KOIZUMI SHIYOUICHIROU , TAKADA YUUJI , TANAKA KIMIHIRO , AOKI EIJI
IPC分类号： H04M11/06 , H04L12/00 , H04L29/10 , H04M11/00
摘要： PURPOSE:To enable the engagement of the synchronous data terminal also on data exchange networks although it is orginally designed to be used on telephone networks.

2. 发明专利

JPS5230304A ASYNCHRONOUS TERMINAL CONNECTION METHOD 失效
公开(公告)号：JPS5230304A
公开(公告)日：1977-03-08
申请号：JP10720475
申请日：1975-09-04
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD , OKI ELECTRIC IND CO LTD , HITACHI LTD
发明人： NANGAKU MASAKAZU , MIKI YASUO , KOIZUMI SHIYOUICHIROU , TAKADA YUUJI , TANAKA KIMIHIRO , AOKI EIJI
IPC分类号： H04M11/06 , H04L12/00 , H04L29/10 , H04M11/00
摘要： PURPOSE:To enable the engagement of the asynchronous data terminal also on data exchange networks although it is primarily designed to be used on telephone networks.

3. 发明专利

JPS5220702A DATA TERMINAL EQUIPMENT 失效
公开(公告)号：JPS5220702A
公开(公告)日：1977-02-16
申请号：JP9699775
申请日：1975-08-09
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： WASHISAWA KENJI , KOIZUMI SHIYOUICHIROU , TAKADA YUUJI
IPC分类号： H04L29/10 , H04L12/00 , H04L29/12
摘要： PURPOSE:Assurance of the reset time after each communication by providing a means of detection of the disconnection with the switchboard and a means of prohibition of the call connection for a certain period after detecting the disconnection.

4. 发明专利

JPS5219902A DATA TERMINAL DEVICE WITH AUTOMATIC CUTTOFF SIGNAL FUNCTION 失效
公开(公告)号：JPS5219902A
公开(公告)日：1977-02-15
申请号：JP9634475
申请日：1975-08-08
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： KASHIWAYAMA KOUSHIN , KOIZUMI SHIYOUICHIROU , TAKADA YUUJI
IPC分类号： H04L1/00 , H04L12/00 , H04L29/08 , H04L29/10 , H04L29/14
摘要： PURPOSE:This data terminal device has the automatic cut-off signal generating circuit that generates a cut-off signal when an error is detected in the control signal received.

5. 发明专利

JPS5220703A DATA TERMINAL EQUIPMENT 失效
公开(公告)号：JPS5220703A
公开(公告)日：1977-02-16
申请号：JP9699875
申请日：1975-08-09
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： NANGAKU MASAKAZU , KOIZUMI SHIYOUICHIROU , TAKADA YUUJI
IPC分类号： H04L29/14 , H04L12/00
摘要： PURPOSE:Economization and miniaturization of the data terminal equipment for digital data exchange network by mounting it on the same bay as of the data circuit terminating equipment.

6. 发明专利

JPS5814644A CLOCK GENERATING CIRCUIT 失效
公开(公告)号：JPS5814644A
公开(公告)日：1983-01-27
申请号：JP11334581
申请日：1981-07-20
申请人： NIPPON ELECTRIC CO
发明人： KOIZUMI SHIYOUICHIROU , YONEHARA AKIHITO
IPC分类号： H03M5/04 , H04L7/02 , H04L7/033 , H04L25/40 , H04L25/52
摘要： PURPOSE:To simplify the constitution of a clock generating circuit, by using the outputs of the two FFs that sample and hold the binary output or the reversed signal of the binary output of a counter with each changing point of the input data, for the preset input of the counter. CONSTITUTION:The rise changing point of the input data given from an input terminal 8 is caused while the binary output QC of a counter 1 having a carry output and a load input is kept at 0. In this case, the output QC and the reverse signal of the QC are stored in the FF3 and FF4 respectively at the rise time point of the input data. When the counter 1 starts counting and the time duration of the output QC is shortened to make the QC advance in phase, the carry output of the counter 1 is delayed by a clock by an FF6 to be turned into the clear signals of the FF3 and FF4. Then the counter 1 is preset by the outputs of the FF3 and FF4 to be reset to the initial state.

7. 发明专利

JPS55125742A TEST CIRCUIT 失效
公开(公告)号：JPS55125742A
公开(公告)日：1980-09-27
申请号：JP3453279
申请日：1979-03-23
申请人： NIPPON ELECTRIC CO
发明人： KOIZUMI SHIYOUICHIROU , YAMAMOTO SEIICHI
IPC分类号： G01R31/00 , H04B17/00 , H04B17/29
摘要： PURPOSE:To enable to minimize the interruption of communication due to test, by reducing the test time through the constitution of the circuit for test added only at test to each circuit of the automatic gain control circuit. CONSTITUTION:At test, the selectors 3, 6, 11, 12 are operated to form the circuit for test. That is, the output of the control voltage production circuit 9 is connected to the judgement circuit 14 with the selector 11 to discriminate whether or not the output of the circuit 9 is within the voltage range expected and output 15 is made, and in the selector 12, the test and control voltage generating circuit 13 producing the output voltage preset is connected to the variable gain circuit 7. Further, the selectors 11, 12 interrupt the input and output of the integration circuit 10, but the circuit 10 holds the control voltage immediately before the test start and plays a role of voltage hold circuit. Next, at the end of test, the selectors 3, 6, 12 are restored, the hold voltage of the circuit 10 is inputted to the circuit 7, and the output signal of the same level as that immediately before the start of test is obtained, the selector 11 is restored after that, and normal communication state is obtained.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式