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1. 发明专利

JPS57137929A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS57137929A
公开(公告)日：1982-08-25
申请号：JP2348981
申请日：1981-02-19
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： YAZAWA KATSUHIKO , OOKAWA KAZUMASA , OOYAMA MINORU , HANAOKA HIDEAKI
IPC分类号： H03M9/00 , G06F13/00 , G06F13/22 , H04L13/10
摘要： PURPOSE:To economically execute a parallel-series data conversion, by installing neither a buffer register nor a shift register in each line corresponding device, but installing the buffer register in a common device. CONSTITUTION:A bit number memory BNM for deciding what ordinal bit of a data DATA0 is sent out to a line corresponding device LC0 or not is read out, and is accumulated in a bit number register BNR. Contents of the bit number memory BNM are read out by the bit number register BNR, a transfer request signal is received from the line corresponding device LC, and a value of the bit number register BNR is updated by a transfer request receiving circuit TREQ. Also, a multiplexer MPX is selected by designation of the bit number register BNR, and the n-th bit of the data DATA0 is loaded on a TLINE and is sent to the line corresponding device LC0.

2. 发明专利

JPS56152051A ASYNCHRONOUS MICROPROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS56152051A
公开(公告)日：1981-11-25
申请号：JP5587280
申请日：1980-04-25
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： OOKAWA KAZUMASA , MURATA KOUICHI , HONGOU IKUO , HANAOKA HIDEAKI
IPC分类号： G06F9/22 , G06F9/26
摘要： PURPOSE:To obtain an efficient micro (mu) program PG control system by reading the same muPG word by continuing to generate the same (mu) address until an expected signal among asynchronizing signals is received and detected by muPG. CONSTITUTION:Selecting circuit 3 and address generating circuit 4 are indicated with a muPG word so that signal expecting register FF2 selects an asynchronizing signal among signals 1 asynchronous with a clock signal from the inside or outside of a data processor. Until the expected signal is received, circuit 4 generates the same address to read the same muPG word continuously and once the expected signal is received, circuit 3 updates the (mu) address to read the next muPG word from control memory CM5. After storing muPG, CM5 informs FF2 of which detected signal makes an advance of the step of muPG via latch register CMIR6 with the muPG word. Thus, there is no unnecessary step in receiving the expected signal and the efficient muPG control system is obtained.

3. 发明专利

JPS5692620A SELECTION SYSTEM OF INPUT*OUTPUT DEVICE 失效
公开(公告)号：JPS5692620A
公开(公告)日：1981-07-27
申请号：JP16972279
申请日：1979-12-26
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： OOKAWA KAZUMASA , NAKAMURA MASANORI , MURAKAMI TOMOSHI , INAGAKI HIROSHI , KOUDA YOSHIFUMI
IPC分类号： G06F11/20 , G06F3/00 , G06F11/16 , G06F13/00
摘要： PURPOSE:To enable to switch the input/output device without changing the device address transmitted from the central processing unit from the software, by setting the act display corresponding to the input/output device to be switched. CONSTITUTION:When starting is made from a central processing unit CC1, a device address is transmitted to an input and output bus 2. Since the same address is assigned to the input/output devices I/O #0-3 and #1-4, a coincidence signal is output from matching circuits MAT8, 9. On the other hand, in a monitor section SUP5, the output of an act display circuit 10 indicating the use of any of I/O sets either I/O #0-3 or #1-4. Accordingly, either one gate is open for AND gates 12, 13 determining the starting of main control sections 11 and 12. That is, the device address is transmitted to start either one of I/O #0-3 or #1-4 from CC1, and one of them is selected at the acting display circuit 10.

4. 发明专利

JPS52101936A DATA CHANNEL DEVICE 失效
公开(公告)号：JPS52101936A
公开(公告)日：1977-08-26
申请号：JP1844076
申请日：1976-02-24
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , OKI ELECTRIC IND CO LTD , FUJITSU LTD
发明人： YAMADA TAKAHIKO , YAMADA SHIGEKI , OOKAWA KAZUMASA , SHIYOUDA AKIO , ICHIURA NOBORU , AWAJI TOSHIO
IPC分类号： G06F9/26 , G06F3/00 , G06F9/22 , G06F13/12
摘要： PURPOSE:To realize a low-cost simple data channel device with the flexibility for extension and modification by concentrating control units in a common channel section and providing a device specify signal in a subchannel device corresponding to each subchannel.

5. 发明专利

JPS58112126A INCORPORATING SYSTEM OF CHANNEL WORD MEMORY 失效
公开(公告)号：JPS58112126A
公开(公告)日：1983-07-04
申请号：JP21567181
申请日：1981-12-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： YASUI YUTAKA , ITOU YOSHITAKA , KAJIZUKA SHIYOUJI , OOKAWA KAZUMASA , TAKI YOSHIHARU
IPC分类号： G06F13/12
摘要： PURPOSE:To minimize a data channel, by deleting an unnecessarily excessive storage capacity out of a channel word memory incorporated into a data channel device and setting the channel word memory to a scale that can store the minimum necessary number of channel words for a practical use. CONSTITUTION:A data channel device 3 collates the received device address with a registered device address through a device address registering/collating part 6. If coincidence is obtained with either one of registered device addresses, the channel word CHWJ corresponding to the coincident registered address within an incorporated channel word memory 5 is read out of a control part 7 and fed to an arithmetic part 8 as well as to be stored in a register. The information stored in the register is replaced with another information as the input/output operation proceeds. Then this stored information is stored at a prescribed region of the memory 5 as soon as a series of control operations is over with a data channel device 30 or 31.

6. 发明专利

JPS58100899A VOICE EDITTING SYSTEM 失效
公开(公告)号：JPS58100899A
公开(公告)日：1983-06-15
申请号：JP19957481
申请日：1981-12-11
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： YASUI YUTAKA , SASAHARA YUUJIROU , OOYAMA MINORU , HANAOKA HIDEAKI , OOKAWA KAZUMASA
IPC分类号： G10L13/04

7. 发明专利

JPS57143993A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPS57143993A
公开(公告)日：1982-09-06
申请号：JP3024981
申请日：1981-03-03
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： SASAHARA YUUJIROU , HARUYAMA NOBUO , OOYAMA MINORU , HANAOKA HIDEAKI , OOKAWA KAZUMASA , YAZAWA KATSUHIKO
IPC分类号： H04L25/40 , H04Q3/545
摘要： PURPOSE:To secure a data transfer speed reducing the amount of hardware of an interface part, by providing a channel system device with a timing pulse generation part which generates timing pulses for reading an optional output of a signal distributor. CONSTITUTION:When new data is set in a signal distributor SD, a channel system device SPS reads transfer data. In this case, the 15th bit is assigned for a synchronizing signal. This synchronizing signal is inputted to a synchronizing signal generation part SYG through a signal receiver REC. When the output of the REC is applied to the SYG, a level detector DET detects the on-to-off fall or off-to-on rise of the synchronizing signal and a timing circuit TIM counts a time from the start of the signal. Then, a pulse generator PG generates the synchronizing signal a prescribed time later, and a timing signal for synchronization is supplied to a register REG to fetch transfer data.

8. 发明专利

JPS56162149A DATA TRANSFER DEVICE 失效
公开(公告)号：JPS56162149A
公开(公告)日：1981-12-12
申请号：JP6407280
申请日：1980-05-16
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： AIZAWA KIYOSHI , OOKAWA KAZUMASA
IPC分类号： G06F13/00 , G06F13/12
摘要： PURPOSE:To transfer data efficiently and economically, by controlling data transfer independently of a microprogram (muPG) after starting a control part by the muPG and by displaying the status detected at the transfer time to generate a muPG address. CONSTITUTION:The signal from a sequence control part 1 of a muPG starts a transfer control part 6 through a memory 3, a register 4, and decoder 5. When started by the muPG, the control part 6 controls the data transfer between a CPU and an I/O independently of the muPG and continues data transfer until a cause of transfer interruption occurs. If a cause of transfer impossibility occurs in the I/O, the control part 6 receives the signal indicating this state from the I/O and displays it on a status register RG9. A muPG address generator 10 tests the state of the RG9 periodically after the control part 6 is started; and when data transfer is interrupted to require another processing, a muPG address corresponding to the state is generated by this generator 10 and is transmitted to the control part 1. The control part 1 controls the system so that the control jumps to the generated address, and required processings are performed.

9. 发明专利

JPS5679322A BUS SELECTION SYSTEM 失效
公开(公告)号：JPS5679322A
公开(公告)日：1981-06-29
申请号：JP15615979
申请日：1979-11-30
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： OOKAWA KAZUMASA , HIROKAWA YUUJI , NISHIDA RIKIO , INAGAKI HIROSHI , KOUDA YOSHIFUMI
IPC分类号： G06F13/14 , G06F3/00 , G06F9/46 , G06F9/52 , G06F13/366 , G06F15/16 , G06F15/177
摘要： PURPOSE:To offer respective processor services equally by facilitating the contention among processors by looking in the detection of whether a request exists, by attaining access to the processor indicated by the value of a sequential counter under microprogram control. CONSTITUTION:To input-output device 20, 0 processor 10 and 1 processor 11 are connected and service requests from processors 10 and 11 are inputted to request detecting circuit 21 via start request signal lines 31 and 32. The transmission and reception of data to and from device 20 are performed via input-output bus lines 33 and 34 connected to bus circuit 22. In addition, sequential counter 23 selecting processor 10 or 11 is made by microcontrol part 24 to count up and request detecting circuit 21 detects a start request, on the basis of the value of counter 23, by the processor number and according to whether the start request signal exists. The signal that this request detecting circut 21 detects is supplied to input-output device 26 via control part 24 to accept the start of bus circuit 22.

10. 发明专利

JPS54115038A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS54115038A
公开(公告)日：1979-09-07
申请号：JP2342078
申请日：1978-02-28
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： DOI AKIHIKO , OOKAWA KAZUMASA , YAMADA SHIGEKI , AMADA HIROYUKI
IPC分类号： G06F9/48
摘要： PURPOSE:To execute service in the order of processing reguest taken place and to perform it econimically, by providing the processing request register, display register after request and the detection circuit for disagreement of the both. CONSTITUTION:The peripheral sections 1,2 producing the processing request in arbitrary time are connected to the processing registration register 4 and the processing request registration register via the bus 9. When the peripheral section 1 requests serive to the control section 7, the processing request register is made by +1 via the operation circuit 6, and the service content of the peripheral section requested is stored in the memory address of the memory 3. On the other hand, the control section 7 detects the disagreement between the processing request registration register 4 and the processing display register 5, and if the exclusive logical sum is other than 0, the serivce is assumed to be present, and the register 5 is made by +1 via the operation circuit 6, the reslt of advance is addressed and accessed to the memory 3, and processing is executed to the peripheral section 1. Thus, the processing request is periodically received and it is sequentially executed.

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