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1. 发明专利

JPH08181685A SYNCHRONIZING CLOCK CIRCUIT 失效
公开(公告)号：JPH08181685A
公开(公告)日：1996-07-12
申请号：JP31956694
申请日：1994-12-22
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP
发明人： AWAJI TOSHIO , MASUOKA HIROYUKI , AKATA MASAO
IPC分类号： H04L7/00 , H04L7/033 , H04Q11/04
摘要： PURPOSE: To allow the circuit to transit to a new phase while preventing instantaneous disturbance in the case of switching of an input clock signal by providing a detecting circuit for pulling out of synchronism providing a re- synchronizing signal to a frame signal generating circuit on the occurrence of out of phase synchronism. CONSTITUTION: A PLL circuit 103 provides a phase clock signal P64K synchronously with a 0 or 1 system reference 64kHz clock signal S64K given by a selection circuit 101 in addition to a prescribed clock frequency signal P16M. An 8KFP generating circuit 105 frequency-divides the signal P64K to generate a 8kHz frame pulse signal 8KFP. A detecting circuit 104 for pulling out of synchronism uses the signal 8KPF, a reference 8kHz clock signal S8K given from a selection circuit 102 to make phase comparison by using the signal P64K given from the PLL circuit 103 to detect pulling out of synchronism. Then a frequency divider circuit 106 frequency-divides a 16MHz clock signal P16M given from the circuit 103 to generate a 2MHz clock signal 2M.

2. 发明专利

JPS62289006A DIGITAL INTERPOLATION FILTER 失效
公开(公告)号：JPS62289006A
公开(公告)日：1987-12-15
申请号：JP13249086
申请日：1986-06-06
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： AKATA MASAO , KOYABU KUNIHIRO , UCHIMURA KUNIHARU , HAYASHI TOSHIO
IPC分类号： H03H17/00 , H03H17/02
摘要： PURPOSE:To decreae number of adders and subtractors by devising the circuit constitution. CONSTITUTION:A data inputted in the sample rate Fs from an input terminal 1 is stored in a register 2 and extracted in the sample rate of 2nfs. The output of the register 2 is inputted to a register 3 operated with a half period shifted from the register 2 in the sample rate (fs) and added by an adder 4. The output of the adder 4 is inputted to an adder 8 by a subtractor 7 and registers 5, 6 operated in. the sample rate 2fs. The output of a register 9 receiving the output of the adder 8 and operated in the sample rate 2nfs is fed to the other input of the adder 8, the output of the adder 8 is inputted to a scaler 11 and outputted from an output terminal 12. A switch 10 inputs the output of the register 5 in a prescribed timing to the register 9 through a scaler 13 to set the register 9 to an initial value.

3. 发明专利

JPS62289015A COUNTER CIRCUIT 失效
公开(公告)号：JPS62289015A
公开(公告)日：1987-12-15
申请号：JP13249186
申请日：1986-06-06
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： KOYABU KUNIHIRO , AKATA MASAO , UCHIMURA KUNIHARU , HAYASHI TOSHIO
IPC分类号： H03K21/08 , H03K23/86
摘要： PURPOSE:To obtain a counter circuit outputting incremental/ decremental count with a small delay by outputting the least significant bit of the incremental count as it is and outputting other bits while a negative logic value is retarded. CONSTITUTION:An output A of an incremental counter circuit 20 consists of n-set of bits ai (i=0,1,2$...,n-1) and the bits a1-an-1 except the least significant bit are fed respectively to 1-bit shift circuits 11-i (i=1, 2, ..., n-1) respectively, which retard the inputted bit ai respectively by a unit time and supply the result to a NOT circuit 10-i. A clock pulse from a clock terminal 30 is fed to the incremental counter circuit 20 and the 1-bit shift circuit 11-i. The least significant bit a0 of the output A and the output of the NOT circuit 10-i are respectively a bit b0 and b1-bn-1 of an output B. Thus, the output B of decremental count is obtained synchronously with the output A of the incremental counter.

4. 发明专利

JPS61154213A OPPOSITE PHASE PRIMARY HIGH PASS FILTER CIRCUIT 失效
公开(公告)号：JPS61154213A
公开(公告)日：1986-07-12
申请号：JP28162984
申请日：1984-12-26
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： AKATA MASAO , SHIBATA OOHIKO , TATSUNO HIDEO
IPC分类号： H03H11/12 , H03H11/04
摘要： PURPOSE:To decrease the capaciatance ratio of capacitors used for the titled circuit when the ratio of a clock frequency to the cut-off frequency of a filter is large by connecting an even number of stages of inverted amplifier circuits including the 2nd switched capacitor in cascade and connecting the connection in cascade with the 1st switched capacitor in the feedback path. CONSTITUTION:An input terminal 1 is connected to an inverting input of an operational amplifier OP1 via a capacitor C0, and an output terminal of the operational amplifier OP1 and the inverting input terminal of the operational amplifier OP1 are connected via a capacitor C1. A common terminal of a switch S1 and a common terminal of a switch S2 are connected via a capacitor C2. The output of the operational amplifier OP1 is given to the input of an inverted amplifier A2, the output of an inverted amplifier A2 is connected to the input of the inverted amplifier A1 and the output of the inverted amplifier A1 is connected to a switched terminal of the switch S1. A switched terminal of the switch S2 and the inverted input terminal of the operational amplifier OP1 are connected and the output of the operational amplifier OP1 and an output terminal 2 are connected.

5. 发明专利

JPH0879268A ATM EXCHANGE 失效
公开(公告)号：JPH0879268A
公开(公告)日：1996-03-22
申请号：JP20973594
申请日：1994-09-02
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP
发明人： DOI YUKIHIRO , TAKAGI KOJI , AKATA MASAO
IPC分类号： H04L1/22 , H04L12/28 , H04Q3/00
摘要： PURPOSE: To simplify confounding control and to perform a cell continuity test of an ATM or the like without specially setting a route with a standby system device of cells for tests or control by realizing system' changeover control only through instruction to a functional block for performing system changeover CONSTITUTION: Instead of a line switching means inside a intersecting selector, filters and a multiplex circuit are provided. Tow filters 301-1 and 301-2 for filtering ATM cells are provided inside one intersecting selector to permit input from both active system and standby system. Also, a function for generating the ATM cells provided with the state information of respective devices in an overhead area inside the functional blocks 10-1 and 10-2 of the active system and the standby system is provided. Thus, when the ATM cells provided with the device state information of an active system device are generated also in the functional block 10-2 of the standby system and transmitted to the intersecting selectors 3-1 and 3-2, since the intersecting selectors pass them through, the ATM cells are passed through from either one of the active system and the standby system.

6. 发明专利

JPS62287716A ANALOG/DIGITAL CONVERTER 失效
公开(公告)号：JPS62287716A
公开(公告)日：1987-12-14
申请号：JP13027286
申请日：1986-06-06
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： AKATA MASAO , KOYABU KUNIHIRO , UCHIMURA KUNIHARU , HAYASHI TOSHIO
IPC分类号： H03M1/12
摘要： PURPOSE:To execute the coefficient multiplication by the shift operation by converting an analog input signal into the 1st digital signal with a prescribed sample rate and adding the 2nd digital signal having a frequency of a zero of a digital filter to the result. CONSTITUTION:A sound band signal inpputted from an input terminal 4 is converted into the 1st digital signal (x) having a sample frequency fso by an oversampling A/D converter 1. A digital addition signal (y) as the 2nd digital signal is added to the digital signal (x) by an adder 5 and inputted to a FIR filter 2 as a digital filter as the 3rd digital signal (z).. The 4th igital signal (a) being the output signal of the FIR filter 2 is inputted to a sample rate conversion 3 as a rate conversion means. The sample rate conversion section 3 thius the digital signal (a) to form a digital signal (b) having a sample frequency fs lower than the sample frequency fso and outputted from an output terminal 6.

7. 发明专利

JPH0879267A TRANSMISSION CONVERGENCE SUB-LAYER MULTIPLEX GENERATION /TERMINATION DEVICE 失效
公开(公告)号：JPH0879267A
公开(公告)日：1996-03-22
申请号：JP20956394
申请日：1994-09-02
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP
发明人： OGAWA TAKESHI , DOI YUKIHIRO , AZUMA ISAO , IMAGAWA HITOSHI , AKATA MASAO , MIURA TAKAO
IPC分类号： H04Q3/00 , H04J3/00 , H04J3/16 , H04L12/64 , H04L12/951 , H04Q11/04 , H04L12/28
摘要： PURPOSE: To reduce a hardware amount by sharing a circuit for generating or terminating a TC layer by plural paths. CONSTITUTION: A TC layer multiplex generation device 120 shares a TC layer computing part 121 for generating the TC layer by the respective paths, stores ATM layer information received for the respective paths in a register 123 and generates the TC layer by using a time division multiplex processing. Also, a TC layer multiplex termination device shares the TC layer computing part 121 for terminating the TC layer by the respective paths, stores the TC layer information received for the respective paths in the register and performs the processing of terminating the TC layer by using the time division multiplex processing every time the respective bytes of the respective paths of an STM highway incoming line arrive.

8. 发明专利

JPS61200760A SUBSCRIBER CIRCUIT 失效
公开(公告)号：JPS61200760A
公开(公告)日：1986-09-05
申请号：JP4139585
申请日：1985-03-01
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： SHIBATA HIROHIKO , AKATA MASAO , TATSUNO HIDEO
IPC分类号： H04M3/06 , H04M19/00
摘要： PURPOSE:To improve the reliability by obtaining a subscriber line interface signal for call reply supervisory of a subscriber from a comparator included in a feeding circuit to use a low-pass filter in common for a response detection circuit thereby decreasing the increase in the hardware. CONSTITUTION:Since subscriber lines 121, 122 are connected to the feeding circuit side by changeover switches 41, 42 during talking, an output of a differential amplifier 8 is zero. On the other hand, at the transmission of a call signal, since the changeover switches 41, 42 open an output of a current source 16, a differential amplifier 15 outputs a prescribed value and a voltage adding a prescribed DC component to an output voltage of the differential amplifier 8 is inputted to a low-pass filter 17. In setting a voltage of a fixed threshold power 11 to a value between a signal peak appearing at an output of the low pass filter 17 before subscriber call reply and a signal peak appearing at subscriber call reply, the polarity is inverted before and after the subscriber reply and a subscriber line interface signal is obtained.

9. 发明专利

JPH07162905A TIME DIVISION MULTIPLEX SWITCH 失效
公开(公告)号：JPH07162905A
公开(公告)日：1995-06-23
申请号：JP31179693
申请日：1993-12-13
申请人： NEC CORP
发明人： AKATA MASAO
IPC分类号： H04Q3/52 , H04Q11/04
摘要： PURPOSE:To provide the time division multiplex time switch composed of T1 steps by constituting the hardware which does not accelerate memory speed and further is not proportional to the square of the multiplicity. CONSTITUTION:A multiframe editing part (CNV) 20 forms multiframes shifted for each frame from input highways (IHW) 11-11 corresponding to input highway banks (IBANK) 31-3j and inputs them to time switches (TSW) 41-4j. The time switches 41-4j change time slot positions for the unit of the multiframe and output them as output highway banks (OBANK) 51-5j, and a multiframe inverse editing part (DCNV) 60 resolves the multiframe into frames corresponding to output highways (OHW) 71-7k.

10. 发明专利

JPH0787156A TIME DIVISION MULTIPLEXING LINE PROCESSOR 失效
公开(公告)号：JPH0787156A
公开(公告)日：1995-03-31
申请号：JP22918293
申请日：1993-09-14
申请人： NEC CORP
发明人： AKATA MASAO
IPC分类号： H04J3/00 , H04L29/04
摘要： PURPOSE:To reduce the capacity of a save memory and to reduce the operation speed by shortening the period of saving and loading of each channel state to and from the save memory. CONSTITUTION:A multiframe conversion part 10 converts N frames on an input time division multiplexing highway 31 to multiple frames, where the same channel is continuous N times, and gives them to a time division multiplexing line processing part 20. Multiple frames which come from the time division multiplexing line processing part 20 and where the same channel is continuous N times are converted to a frame form on an output time division multiplexing highway 32 and are outputted to an output time division multiplexing highway 32.

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