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1. 发明专利

JP2003188714A MULTI-INPUT LOGIC GATE 审中-公开
公开(公告)号：JP2003188714A
公开(公告)日：2003-07-04
申请号：JP2001386875
申请日：2001-12-20
申请人： NTT ELECTRONICS CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： SHINPO YUKIO , YAMAGISHI AKIHIRO , TSUKAHARA TSUNEO
IPC分类号： H03K19/20 , H03K19/094 , H03K19/0944
摘要： PROBLEM TO BE SOLVED: To provide a CMOS multi-input logic gate which can be operated with a small signal amplitude and can reduce power consumption. SOLUTION: The multi-input logic gate has a current source, first and second resistors in which each of one terminal is connected to a power source, m pieces (m is an integer of ≥2) of transistors in which respective sources are connected in parallel to the current source and respective drains are connected in parallel to the other terminal of the first resistor, and m pieces of transistors in which sources and drains are connected in series between the current source and the other terminal of the second resistor. Thus m sets of differential input signals are respectively inputted to the gates of the parallel connected transistors and the gates of the serially connected transistors and outputted from the other terminal of each of the first resistor and the second resistor as differential signals. COPYRIGHT: (C)2003,JPO

2. 发明专利

JPH11284497A PROGRAMMABLE DELAY GENERATOR AND APPLICATION CIRCUIT USING THE SAME 失效
公开(公告)号：JPH11284497A
公开(公告)日：1999-10-15
申请号：JP1549599
申请日：1999-01-25
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NOSAKA HIDEYUKI , MINAGAWA AKIRA , YAMAGUCHI AKIRA , YAMAGISHI AKIHIRO
IPC分类号： H03K5/04 , H03K5/00 , H03K5/135
摘要： PROBLEM TO BE SOLVED: To provide a programmable delay generator, with which the control of a circuit constant can be dispensed with and the delay time of a fraction capable of setting both a numerator and a denominator can be generated with high accuracy, and a frequency synthesizer capable of generating a low-spurious output signal with no control. SOLUTION: For this programmable delay generator, a threshold voltage generating circuit 20A for generating a threshold voltage Vk proportional to set data K and a ramp wave generating circuit 10A for generating a ramp wave voltage Vs proportional to set data S are provided in the same circuit configuration, the delay time of a fraction K/S is generated, and effects exerted upon the delay time by the circuit constants of both the circuits are canceled. In addition, the threshold voltage generating circuit 20A and the ramp wave generating circuit 10A are operated synchronously with an external clock. The frequency synthesizer uses such a programmable delay generator as a means for phase interpolation at a direct digital synthesizer. Furthermore, a multiplier, duty ratio converting circuit and PLL frequency synthesizer are enabled as the application circuit for the programmable delay generator.

3. 发明专利

JPH1197936A DIRECT DIGITAL SYNTHESIZER 失效
公开(公告)号：JPH1197936A
公开(公告)日：1999-04-09
申请号：JP25627497
申请日：1997-09-22
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NOSAKA HIDEYUKI , YAMAGISHI AKIHIRO
IPC分类号： H03K3/02 , H03B28/00
摘要： PROBLEM TO BE SOLVED: To reduce power consumption by reducing the circuit scale of, specially, a data converting circuit in the circuit configuration of a direct digital synthesizer. SOLUTION: This direct digital synthesizer is provided with an accumulator 1 which inputs frequency setting data and a clock having a period T and accumulates and adds the frequency setting data K by pulses of the clock, a data converting circuit 2 which calculates the complement N of '1' of the output data of the accumulator 1, a delay circuit 6 which inputs the frequency setting data K as 2nd delay data and the most significant digit bit of the output data of the accumulator 1 as a trigger signal and outputs a pulse a time ((N+1)/K).T after the input of the trigger signal, and a pulse generator 7 which generates a pulse at a rise or fall of the delay circuit 6.

4. 发明专利

JPH1127050A VOLTAGE-TO-FREQUENCY CONVERTER AND FREQUENCY SYNTHESIZER USING THE CONVERTER 失效
公开(公告)号：JPH1127050A
公开(公告)日：1999-01-29
申请号：JP19073897
申请日：1997-07-02
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NOSAKA HIDEYUKI , YAMAGISHI AKIHIRO
IPC分类号： H03L7/099 , H03B28/00
摘要： PROBLEM TO BE SOLVED: To provide a voltage/frequency converter which can secure the absolute accuracy of output frequency with no adjustment despite a simple circuit constitution, has high linearity between the input voltage and the output frequency and also contains no phase jitter in the output signal by performing switching between an integration period and a leak period synchronously with a clock and also using the output of a comparator as a one-shot trigger. SOLUTION: This converter consists of an integrator 41 which switches and integrates plural input voltage levels via a switch, a one-shot circuit 7 which immediately outputs a pulse by the output of a comparator 4 that compares the output voltage of the integrator 41 with threshold voltage Vs, and a D-FF 13 which inputs the output of the comparator 4 and uses a clock pulse as a trigger. Then the signal of the D-FF 13 that is synchronized with a clock is inputted to the switch to synchronize the switch timing of the input voltage with the clock. Meanwhile, the circuit 7 performs a direct trigger by the output of the comparator 4 which is asynchronous with the clock. Thus, the spurious characteristic is secured with a satisfactory output signal.

5. 发明专利

JPH08130414A SYNTHESIZER CIRCUIT 失效
公开(公告)号：JPH08130414A
公开(公告)日：1996-05-21
申请号：JP26873294
申请日：1994-11-01
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAGISHI AKIHIRO , ISHIKAWA MASAYUKI
IPC分类号： H03B28/00
摘要： PURPOSE: To reduce the required capacity of a ROM, to reduce circuit scale and to reduce power consumption by providing three devices for respectively generating specified data, and providing the waveform data of a sine wave by adding the data of these three devices. CONSTITUTION: A bit inverter 2 is composed of an EX-OR step. The outputs of the bit inverter 2 are data corresponding to the phases from '0' to π/2. With these data as inputs, the sine waveform data corresponding to the phases from '0' to π/2 are separately generating, calculating following three data, data [1:M-1] are data to be linearly increased from the value of sine waveform data at the time of phase '0', data B (B[1:M-4]) are data of the 1/4 value of data A at the phases from '0' to π/4, and data C (C[1:M-4]) are data for correction. These three kinds of amplitude data are added by a full adder 5 so that the half-wave rectified waveform of a sine wave can be provided.

6. 发明专利

JP2003188716A TWO-MODULUS PRESCALER CIRCUIT 审中-公开
公开(公告)号：JP2003188716A
公开(公告)日：2003-07-04
申请号：JP2001386873
申请日：2001-12-20
申请人： NIPPON TELEGRAPH & TELEPHONE , NTT ELECTRONICS CORP
发明人： YAMAGISHI AKIHIRO , TSUKAHARA TSUNEO , SHINPO YUKIO
IPC分类号： H03K21/00 , H03K23/64 , H03K23/66
摘要： PROBLEM TO BE SOLVED: To make it possible to be operated with a small signal amplitude and reduce power consumption in a two-modulus prescaler circuit available for a frequency synthesizer or the like. SOLUTION: The prescaler circuit is provided with n pieces of (n≥3) DFF and first and second multi-input logic gates having at least two inputs and configured to connect the output terminal of the first multi-input logic gate to the data input terminal of the first DFF, to respectively connect the output terminals of first to (n-2)th DFF to the data input terminals of the second to (n-1)th DFF, to connect the output terminal of the (n-1)th DFF and the output terminal of the n-th DFF to the input terminal of the first multi-input logic gate, to connect the output terminal of the (n-1)th DFF to the second multi-input logic gate, to input a switching signal thereto and to connect the output terminal of the second multi-input logic gate to the data input terminal of the n-th DFF, and all the connections are connection to use differential signals. COPYRIGHT: (C)2003,JPO

7. 发明专利

JP2001352218A VOLTAGE-CONTROLLED OSCILLATOR 失效
公开(公告)号：JP2001352218A
公开(公告)日：2001-12-21
申请号：JP2000172959
申请日：2000-06-09
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAGISHI AKIHIRO , UGAJIN MAMORU , TSUKAHARA TSUNEO
IPC分类号： H03B7/06 , H03B5/08 , H03B5/12 , H03C3/22 , H03L7/06 , H04L27/10
摘要： PROBLEM TO BE SOLVED: To widen the linear range of conversion characteristics of a resonance type voltage-controlled oscillator by a CMOS process. SOLUTION: This oscillator has a resonance circuit 201, a negative resistance circuit 202, and varactor elements 2031 to 2034 and a control voltage is shifted by a specific value at each time through a level shift circuit 206 and applied to the varactor elements to expand the linear range of the oscillation frequency to the control voltage.

8. 发明专利

JP2000114937A MULTIPLIER 失效
公开(公告)号：JP2000114937A
公开(公告)日：2000-04-21
申请号：JP33218098
申请日：1998-11-24
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAGUCHI AKIRA , MURAGUCHI MASAHIRO , NOSAKA HIDEYUKI , MINAGAWA AKIRA , YAMAGISHI AKIHIRO
IPC分类号： H03K5/00
摘要： PROBLEM TO BE SOLVED: To sufficiently suppress the output level of an unnecessary frequency component without the use of a filter circuit by level-converting an input signal into two signals where at least one signal becomes the signal of a rectangular wave, outputting them, multiplying the two signals which are level-converted and outputting them. SOLUTION: A multiplier is provided with a level shift circuit 2 which level- coverts an input signal into two signals where at least one signal becomes the signal of a rectangular wave and outputs them and a Gilbert cell-type multiplier 3 multiplying the two signals outputted from the level circuit 2 and outputting them. Output voltage Vout is obtained as the multiplication output of input voltages V1 and V2 and multiplication output can correspondingly be obtained. Since an offset owing to a DC voltage component actually occurs, a basic component and the higher harmonic component of an odd-order generate. Thus, one input signal V1 of the Gilbert cell-type multiplier 3 is left to be an outer input signal as it is and an input signal V2 is inputted as the rectangular wave.

9. 发明专利

JPH1127049A FREQUENCY SYNTHESIZER 失效
公开(公告)号：JPH1127049A
公开(公告)日：1999-01-29
申请号：JP19073997
申请日：1997-07-02
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NOSAKA HIDEYUKI , NAKAGAWA TADAO , YAMAGISHI AKIHIRO
IPC分类号： H03L7/197 , H03B28/00 , H03K3/02 , H03L7/08
摘要： PROBLEM TO BE SOLVED: To provide a frequency synthesizer which can operate at high frequency and with small power consumption by replacing the operation of an accumulator of a direct digital synthesizer with the operation of a simple analog circuit consisting of an integrator and a comparator. SOLUTION: An integrator 12 is reset by the reset input of the digital data N and M, the threshold voltage VS and a clock fCLK and functions to increase the output voltage with a tilt proportional to N or N-M and according to a high or low logical level of the control input. A comparator 4 compares the output voltage of the integrator 12 with the voltage VS to perform switching between the high and low logical levels of output. A multivibrator 15 provides the output frequency by using the output of the comparator 4 as a trigger. A D-FF 13 sends the output of the comparator 4 to the control input of the integrator 12 as data by using the clock fCLK as a trigger. Then a divider 16 sends the divided output to the integrator 12.

10. 发明专利

JPH08204529A CURRENT SWITCH CIRCUIT AND D/A CONVERTER 失效
公开(公告)号：JPH08204529A
公开(公告)日：1996-08-09
申请号：JP2621095
申请日：1995-01-20
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAGISHI AKIHIRO , ISHIKAWA MASAYUKI
IPC分类号： H03M1/08 , H03K17/16 , H03K17/687
摘要： PURPOSE: To reduce switching noise caused by a parasitic capacitance by connecting a transistor whose gate and source are connected together to the output terminal of the current switch circuit and applying a signal in complementary with a control signal to its gate. CONSTITUTION: A switching transistor(TR) 1 (2) selects the output current of a constant current source CS to a positive output terminal 10p and negative output terminal 10n. The gate voltage of the TR T1 is changed to supply a switch current ISW from the gate of the TR T1 to the positive output terminal 10p through a parasitic capacitance Cgds1 between the gate and source in a transient state. On the other hand, a control signal P is fed to the gate of the TR T1 and the inverse of the signal P is fed to the gate of a TR T3 to absorb a current flowing to the parasitic capacitance Cgs1 of the TR T1 by the gate of the TR T3 thereby cancelling switching noise.

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