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1. 发明专利

JPH03290749A DATA TRANSFER CIRCUIT 失效
公开(公告)号：JPH03290749A
公开(公告)日：1991-12-20
申请号：JP9166290
申请日：1990-04-06
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SUZUKI YUTAKA , TAKAHASHI TOSHIYUKI
IPC分类号： G06F13/28
摘要： PURPOSE:To attain the transfer of data without stopping the working of an arithmetic circuit as much as possible for a digital signal processing circuit containing a memory and an arithmetic circuit set in parallel with each other by setting the transfer cycle number at 1/N on an internal data bus where N pieces of data are buffed by an input/output circuit. CONSTITUTION:An input/output circuit 2 is provided with registers 21 - 24 are performs the buffing operations between an input/output port 1 and the internal data buses 611 - 614. That is, four pieces of input data are stored in a data input state and the data are stored in all registers. At the same time, a queuing state is kept until the buses 611 - 614 become idle. In a data output state, the data sent from the buses 611 - 614 are stored and then outputted successively to an external memory, etc., through the port 1. Therefore the working cycle number of the internal data bus can be reduced down to 1/4 for transfer of data. Thus a memory and an arithmetic circuit are set in parallel with each other. Then the transfer cycle number is decreased in response to the parallel degree and the internal data buses are used by the arithmetic circuit.

2. 发明专利

JPH031692A INTER-MULTI-POINT VIDEO COMMUNICATION SYSTEM 失效
公开(公告)号：JPH031692A
公开(公告)日：1991-01-08
申请号：JP13703689
申请日：1989-05-29
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SUZUKI YUTAKA , TAJIRI TETSUO , TAKAHASHI TOSHIYUKI
IPC分类号： H04N7/15
摘要： PURPOSE:To attain inter-multi-point communication using a video and audio signal without use of a central control unit by connecting an optional set among N-set of inter-multi-point video communication equipments directly to other two equipments and providing a signal synthesis means. CONSTITUTION:The communication from video communication equipment T1 to a video communication equipment T2, from video communication equipment T2 to a video communication equipment T3,..., from video communication equipment Tn-1 to a video communication equipment Tn, and from video communication equipment Tn to a video communication equipment T1 is attained in N-set (N is an integral number being 3 or over). Then the equipment T1 synthesizes the signal generated from its own equipment with a signal received by the equipment Tn and outputs the result to the equipment T2. The video communication is applied among 3 or over of points without interposing of the central controller and the utilizing efficiency of the multi-point communication line where the video communication equipments are interconnected is improved. Since no basic restriction to the number of equipments exists, communication is attained with an optional equipment number, then the communication cost of each equipment is constant independently of the number of equipments and the deterioration in the communication quality is minimized.

3. 发明专利

JPH01207826A MICRO CONTROL SYSTEM 失效
公开(公告)号：JPH01207826A
公开(公告)日：1989-08-21
申请号：JP3357788
申请日：1988-02-16
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SUZUKI YUTAKA , KURODA HIDEO , TAJIRI TETSUO , TAKAHASHI TOSHIYUKI
IPC分类号： G06F9/28 , G06F9/22
摘要： PURPOSE:To attain an optimization as the control mechanism of a high speed signal processor to use a parallel processing by executing the efficient execution control of plural modules at the bit width of a limited microinstruction. CONSTITUTION:In a module 1, a microinstruction inputted from a micro instruction bus 4 is decoded by a decoder 11. When the microinstruction is a load type instruction and a field to indicate a destination module coincides with the module 1, the command parameter of the microinstruction is written to either of microinstruction registers 12 indicated by the field. When the micro instruction is an execution type instruction and the module bit of a bit column field is active, the start-up the hang-up of an action is indicated to a command set in the register 12 indicated by the field. In case of the start-up, the command is outputted from the register 12 and is supplied to an operating unit 13, and the selection of an operating classification and the control of a data input terminal 14 are executed.

4. 发明专利

JPH01194695A DIGITAL PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH01194695A
公开(公告)日：1989-08-04
申请号：JP1744488
申请日：1988-01-29
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KURODA HIDEO , TSUCHIYA TOSHIO , SUZUKI YUTAKA , TAJIRI TETSUO , YANAKA KAZUHISA , TAKAHASHI TOSHIYUKI
IPC分类号： H04N9/64 , H04N9/45 , H04N9/66 , H04N11/04
摘要： PURPOSE:To eliminate the limit of a sampling frequency and the unstability of a circuit by accumulating the basic address signal of a phase generating circuit for 2piXN/M every time a sampling clock T is increased by one and outputting the accumulation result. CONSTITUTION:A phase synchronizing circuit 100 pays attention to a color sub-carrier only out of the digitized NTSC signals which is the output of an A/D converting circuit 4, a phase comparator 101 compares the phase of the color sub-carrier with the output of a signal generating circuit 102 and a phase correcting quantity determining circuit 106 determines the phase correcting quantity for the phase synchronization. The signal generating circuit 102 generates the value of SINtheta.COStheta by the phase for respective sampling clocks (T) based on the output of a phase generating circuit 104 basicly, and is operated in accordance with the phase to correct the phase only by the value instructed by the phase correcting quantity determining circuit 106 for the output of a phase generating circuit 104, namely, the output of a phase correcting circuit 105. Namely, the expression is executed by a phase log2M bit of the color sub-carrier, N is accumulated at every sample, in short, the sampling clock of 13.5MHz and a lower order log2M bit the accumulation result becomes the output of the phase generating circuit 104.

5. 发明专利

JPH0265389A DIGITAL PICTURE SYNTHESIZING CIRCUIT 失效
公开(公告)号：JPH0265389A
公开(公告)日：1990-03-06
申请号：JP21765088
申请日：1988-08-30
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAKAHASHI TOSHIYUKI , KURODA HIDEO
IPC分类号： H04N5/265 , H04N9/74
摘要： PURPOSE:To reduce the circuit scale of an LSI by modulating the color sub carrier of a phase, which is same as the color sub carrier of a digital NTSC signal for master picture, by a digital color difference signal for slave picture. CONSTITUTION:In a master picture constituting circuit 10, a modulating circuit 16 modulates the color sub carrier, which is generated in an internal part, by master picture digital color difference signals C1 and C2 which are respectively inputted from input terminals 12 and 13. Then, a carrier chrominance signal is outputted. A master picture digital luminance signal, which is inputted from an input terminal 11, and the above mentioned carrier chrominance signal are synthesized by a synthesizing circuit 17 and the digital NTSC signal for master picture is outputted from a terminal 51. On the other hand, the three signals of a slave picture digital luminance signal Y', which is inputted from an input terminal 21, and slave picture digital color difference signals C1' and C2', which are inputted from input terminals 22 and 23, are written to a frame memory 25.

6. 发明专利

JPH01205353A SYSTEM AND CIRCUIT FOR CONTROLLING MULTI-BANK MEMORY 失效
公开(公告)号：JPH01205353A
公开(公告)日：1989-08-17
申请号：JP2893088
申请日：1988-02-12
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SUZUKI YUTAKA , KURODA HIDEO , TAJIRI TETSUO , TAKAHASHI TOSHIYUKI
IPC分类号： G06F12/06
摘要： PURPOSE:To attain the memory access of a window system in which overhead for control is less by connecting data input/output port to memory banks by means of address signals in a previously designated window. CONSTITUTION:Input/output data signals D0-D3 in respective memory banks MB0-MB3 are connected to a switch circuit network SWN. Internal window address signals Wj corresponding to respective data input/output ports P0-P3 are previously stored in registers W0-W3. A bank address signal B and the address signals Wj in switching circuits SW0-SW3 are added by adders AD0-AD3 and the modulo values are outputted as the switching control signals Sb0-Sb3 of the circuits SW0-SW3. As a result, a j-th data input/output port Pi is connected to the banks MB0-MB3 of B+Wj.

7. 发明专利

JPH01207864A INTER-MODULE CONNECTION CONTROL CIRCUIT 失效
公开(公告)号：JPH01207864A
公开(公告)日：1989-08-21
申请号：JP3350188
申请日：1988-02-16
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SUZUKI YUTAKA , KURODA HIDEO , TAJIRI TETSUO , TAKAHASHI TOSHIYUKI
IPC分类号： G06F13/36 , G06F13/20 , G06F15/16 , G06F15/177 , G06F15/80
摘要： PURPOSE:To relax the limit of a connection channel by providing first and second channels to input and output a signal to an adjacent module and a third channel to input and output the signal to the bus in a circumferential direction and selecting the channel with a control signal. CONSTITUTION:When the output request signal ORa of a module 100 is active and the input request signal IRb of an adjacent module 200 is passive, an output signal Ya is connected to a circumferential bus 30 and no connection is executed under conditions except this. A signal is obtained by a gate 104 and it is attained by controlling to make a buffer 102 into an action condition in case of the active and into a high impedance condition in case of the passive. When the input request signal IRa of the module 100 is active and the output request signal ORb of the module 200 is passive, a channel Br from the bus 30 is selected and a channel Qr is selected under the other conditions. Thus, the limit of the channel is relaxes by controlling the connection condition of the channel with the combination of the control signals.

8. 发明专利

JP2014016314A Electric pole inclination measuring device and fixture for the same 审中-公开
标题翻译：电子内胆测量装置及其相关的固定装置
公开(公告)号：JP2014016314A
公开(公告)日：2014-01-30
申请号：JP2012155709
申请日：2012-07-11
申请人： Nippon Telegraph & Telephone East Corp , 東日本電信電話株式会社 , Ntt Higashinihon-Kanagawa Co Ltd , 株式会社Ntt東日本−神奈川
发明人： OKAWA TAKATSUGU , TAKAHASHI TOSHIYUKI , HIROSE YASUKI , SERIZAWA YOSHIO
IPC分类号： G01C9/00 , H02G1/02
摘要： PROBLEM TO BE SOLVED: To accurately and easily measure a degree of an inclination of an electric pole.SOLUTION: An electric pole inclination measuring device 10 comprises a fixture 20 having a guide member 21 with a V-shaped cross section and a base member 22 perpendicular to the guide member 21. Because the guide member 21 of the fixture 20 has the V-shaped cross section, the same can be arranged parallel to an axial line of an electric pole 100 with tip sections of respective plate members 21a and 21b placed against an outer periphery of the electric pole 100. Thus, an inclination angle of the electric pole 100 can be highly accurately measured with a horizontal measuring device 30 on the base member 22.
摘要翻译：要解决的问题：准确和容易地测量电极的倾斜度。解决方案：电极倾斜测量装置10包括具有V形横截面的引导构件21和基座构件22的固定装置20 由于固定装置20的引导构件21具有V形横截面，所以可以平行于电极100的轴线排列相应的板构件21a和21b的末端部分抵靠电极100的外周。因此，可以通过基底构件22上的水平测量装置30高精度地测量电极100的倾斜角度。

9. 发明专利

JPH02206292A CODE CONVERTING CIRCUIT FOR VARIABLE LENGTH CODE 失效
公开(公告)号：JPH02206292A
公开(公告)日：1990-08-16
申请号：JP2584189
申请日：1989-02-06
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAKAHASHI TOSHIYUKI , KURODA HIDEO , SUZUKI YUTAKA
IPC分类号： H04N19/00 , H04N19/42 , H04N19/70 , H04N19/85 , H04N19/91
摘要： PURPOSE:To make unnecessary the effective bits of a variable length code as an input and to simplify a circuit by adding more than one discriminatable additional bits after the effective data of a variable length encoded word at a different bit length, making the lengths fixed, and detecting and eliminating the additional bits from the fixed length encoded word. CONSTITUTION:When (n)-bit variable length codes are inputted from variable length code input terminals DI1 to DIn, the bits of an input shift register 14 are shifted by one to a high-order side at the timing of a clock 2. A comparing circuit 15 inputs one discriminatable additional bit or more other than the highest-order bit of the input shift register 14 in units of a clock, and the circuit 15 detects a pattern. Further an output shift register 17 shifts the bits by one to the high-order side, and simultaneously inputs one bit outputted from the input shift register 14 to the lowest-order bit. A counter 16 counts the bits until the data of the output shift register 17 amount to the (n) bits, and when they amount to the (n) bits, the data of the output shift register 17 are outputted from output terminals DO1 DOn in parallel.

10. 发明专利

JPH02107086A MOTION VECTOR SEARCHING SYSTEM 失效
公开(公告)号：JPH02107086A
公开(公告)日：1990-04-19
申请号：JP25954988
申请日：1988-10-17
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAKAHASHI TOSHIYUKI , KURODA HIDEO
IPC分类号： H04N19/50 , H04N19/105 , H04N19/136 , H04N19/137 , H04N19/176 , H04N19/189 , H04N19/196 , H04N19/423 , H04N19/503 , H04N19/51 , H04N19/533
摘要： PURPOSE:To curtail the processing quantity by detecting the presence and absence of a motion in units of the block by a pretreatment part and controlling a motion compensating processing with the result. CONSTITUTION:At a pretreatment circuit 2, a picture signal inputted from a signal input terminal 1 and the preceding encoded picture signal in an input buffer 3 are read, and the difference between two picture signals is operated to a block unit for compensating a motion. When an arithmetic result is less than a certain constant threshold, 'No motion' is judged, and a motion compensating forecasting circuit 4, when a motion compensating control signal outputted from the pretreatment circuit 2 displays 'no motion', outputs a '0' vector from a motion vector output terminal 7. Thus, since the motion compensating processing is not executed to the block without action, the processing quantity of DSP(Digital Signal Processor) can be drastically curtailed.

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